diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/svtypes/struct_array.sv | 191 | ||||
| -rw-r--r-- | tests/various/cellarray_array_connections.ys | 45 |
2 files changed, 236 insertions, 0 deletions
diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv index 873f7befd..739f202ab 100644 --- a/tests/svtypes/struct_array.sv +++ b/tests/svtypes/struct_array.sv @@ -39,4 +39,195 @@ module top; always_comb assert(s2==80'hFC00_4200_0012_3400_FFFC); + // Same as s2, but with little endian addressing + struct packed { + bit [0:7] [7:0] a; // 8 element packed array of bytes + bit [0:15] b; // filler for non-zero offset + } s3; + + initial begin + s3 = '0; + + s3.a[5:6] = 16'h1234; + s3.a[2] = 8'h42; + + s3.a[0] = '1; + s3.a[0][1:0] = '0; + + s3.b = '1; + s3.b[14:15] = '0; + end + + always_comb assert(s3==80'hFC00_4200_0012_3400_FFFC); + + // Same as s3, but with little endian bit addressing + struct packed { + bit [0:7] [0:7] a; // 8 element packed array of bytes + bit [0:15] b; // filler for non-zero offset + } s3_b; + + initial begin + s3_b = '0; + + s3_b.a[5:6] = 16'h1234; + s3_b.a[2] = 8'h42; + + s3_b.a[0] = '1; + s3_b.a[0][6:7] = '0; + + s3_b.b = '1; + s3_b.b[14:15] = '0; + end + + always_comb assert(s3_b==80'hFC00_4200_0012_3400_FFFC); + + struct packed { + bit [0:7] [0:1] [0:3] a; + bit [0:15] b; // filler for non-zero offset + } s3_lll; + + initial begin + s3_lll = '0; + + s3_lll.a[5:6] = 16'h1234; + s3_lll.a[2] = 8'h42; + + s3_lll.a[0] = '1; + s3_lll.a[0][1][2:3] = '0; + + s3_lll.b = '1; + s3_lll.b[14:15] = '0; + end + + always_comb assert(s3_lll==80'hFC00_4200_0012_3400_FFFC); + + struct packed { + bit [0:7] [1:0] [0:3] a; + bit [0:15] b; // filler for non-zero offset + } s3_lbl; + + initial begin + s3_lbl = '0; + + s3_lbl.a[5:6] = 16'h1234; + s3_lbl.a[2] = 8'h42; + + s3_lbl.a[0] = '1; + s3_lbl.a[0][0][2:3] = '0; + + s3_lbl.b = '1; + s3_lbl.b[14:15] = '0; + end + + always_comb assert(s3_lbl==80'hFC00_4200_0012_3400_FFFC); + + struct packed { + bit [0:7] [0:1] [3:0] a; + bit [0:15] b; // filler for non-zero offset + } s3_llb; + + initial begin + s3_llb = '0; + + s3_llb.a[5:6] = 16'h1234; + s3_llb.a[2] = 8'h42; + + s3_llb.a[0] = '1; + s3_llb.a[0][1][1:0] = '0; + + s3_llb.b = '1; + s3_llb.b[14:15] = '0; + end + + always_comb assert(s3_llb==80'hFC00_4200_0012_3400_FFFC); + +`ifndef VERIFIC + // Note that the tests below for unpacked arrays in structs rely on the + // fact that they are actually packed in Yosys. + + // Same as s2, but using unpacked array syntax + struct packed { + bit [7:0] a [7:0]; // 8 element unpacked array of bytes + bit [15:0] b; // filler for non-zero offset + } s4; + + initial begin + s4 = '0; + + s4.a[2:1] = 16'h1234; + s4.a[5] = 8'h42; + + s4.a[7] = '1; + s4.a[7][1:0] = '0; + + s4.b = '1; + s4.b[1:0] = '0; + end + + always_comb assert(s4==80'hFC00_4200_0012_3400_FFFC); + + // Same as s3, but using unpacked array syntax + struct packed { + bit [7:0] a [0:7]; // 8 element unpacked array of bytes + bit [0:15] b; // filler for non-zero offset + } s5; + + initial begin + s5 = '0; + + s5.a[5:6] = 16'h1234; + s5.a[2] = 8'h42; + + s5.a[0] = '1; + s5.a[0][1:0] = '0; + + s5.b = '1; + s5.b[14:15] = '0; + end + + always_comb assert(s5==80'hFC00_4200_0012_3400_FFFC); + + // Same as s5, but with little endian bit addressing + struct packed { + bit [0:7] a [0:7]; // 8 element unpacked array of bytes + bit [0:15] b; // filler for non-zero offset + } s5_b; + + initial begin + s5_b = '0; + + s5_b.a[5:6] = 16'h1234; + s5_b.a[2] = 8'h42; + + s5_b.a[0] = '1; + s5_b.a[0][6:7] = '0; + + s5_b.b = '1; + s5_b.b[14:15] = '0; + end + + always_comb assert(s5_b==80'hFC00_4200_0012_3400_FFFC); + + // Same as s5, but using C-type unpacked array syntax + struct packed { + bit [7:0] a [8]; // 8 element unpacked array of bytes + bit [0:15] b; // filler for non-zero offset + } s6; + + initial begin + s6 = '0; + + s6.a[5:6] = 16'h1234; + s6.a[2] = 8'h42; + + s6.a[0] = '1; + s6.a[0][1:0] = '0; + + s6.b = '1; + s6.b[14:15] = '0; + end + + always_comb assert(s6==80'hFC00_4200_0012_3400_FFFC); +`endif + endmodule diff --git a/tests/various/cellarray_array_connections.ys b/tests/various/cellarray_array_connections.ys new file mode 100644 index 000000000..ef36a9a45 --- /dev/null +++ b/tests/various/cellarray_array_connections.ys @@ -0,0 +1,45 @@ +# Regression test for #3467 +read_verilog <<EOT + +module bit_buf ( + input wire bit_in, + output wire bit_out +); + assign bit_out = bit_in; +endmodule + +module top ( + input wire [3:0] data_in, + output wire [3:0] data_out +); + + wire [3:0] data [0:4]; + + assign data[0] = data_in; + assign data_out = data[4]; + + genvar i; + generate + for (i=0; i<=3; i=i+1) begin + bit_buf bit_buf_instance[3:0] ( + .bit_in(data[i]), + .bit_out(data[i + 1]) + ); + end + endgenerate +endmodule + +module top2 ( + input wire [3:0] data_in, + output wire [3:0] data_out +); + assign data_out = data_in; +endmodule + +EOT + +hierarchy +proc + +miter -equiv -make_assert -flatten top top2 miter +sat -prove-asserts -verify miter |