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-rw-r--r--tests/various/param_struct.ys3
-rw-r--r--tests/various/struct_access.sv43
-rw-r--r--tests/various/struct_access.ys5
-rw-r--r--tests/verilog/struct_access.sv5
4 files changed, 51 insertions, 5 deletions
diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys
index 6d7a7c6ad..b8de67968 100644
--- a/tests/various/param_struct.ys
+++ b/tests/various/param_struct.ys
@@ -41,8 +41,7 @@ always_comb begin
assert(j == 1'b1);
assert(k == 1'b0);
assert(l == 3'b111);
-// TODO: support access to whole sub-structs and unions
-// assert(m == 2'b10);
+ assert(m == 2'b10);
assert(u == 5'b11001);
end
endmodule
diff --git a/tests/various/struct_access.sv b/tests/various/struct_access.sv
new file mode 100644
index 000000000..d41a7114f
--- /dev/null
+++ b/tests/various/struct_access.sv
@@ -0,0 +1,43 @@
+module dut();
+typedef struct packed {
+ logic a;
+ logic b;
+} sub_sub_struct_t;
+
+typedef struct packed {
+ sub_sub_struct_t c;
+} sub_struct_t;
+
+typedef struct packed {
+ sub_struct_t d;
+ sub_struct_t e;
+} struct_t;
+
+parameter struct_t P = 4'b1100;
+
+localparam sub_struct_t f = P.d;
+localparam sub_struct_t g = P.e;
+localparam sub_sub_struct_t h = f.c;
+localparam logic i = P.d.c.a;
+localparam logic j = P.d.c.b;
+localparam x = P.e;
+localparam y = x.c;
+localparam z = y.a;
+localparam q = P.d;
+localparam n = q.c.a;
+
+always_comb begin
+ assert(P == 4'b1100);
+ assert(f == 2'b11);
+ assert(g == 2'b00);
+ assert(h == 2'b11);
+ assert(i == 1'b1);
+ assert(j == 1'b1);
+ assert(x == 2'b00);
+ assert(y == 2'b00);
+ assert(x.c == 2'b00);
+ assert(y.b == 1'b0);
+ assert(n == 1'b1);
+ assert(z == 1'b0);
+end
+endmodule
diff --git a/tests/various/struct_access.ys b/tests/various/struct_access.ys
new file mode 100644
index 000000000..2282edd92
--- /dev/null
+++ b/tests/various/struct_access.ys
@@ -0,0 +1,5 @@
+read_verilog -sv struct_access.sv
+hierarchy
+proc
+opt
+sat -verify -seq 1 -prove-asserts -show-all
diff --git a/tests/verilog/struct_access.sv b/tests/verilog/struct_access.sv
index f13b8dd51..bc91e3f01 100644
--- a/tests/verilog/struct_access.sv
+++ b/tests/verilog/struct_access.sv
@@ -77,9 +77,8 @@ module top;
`CHECK(s.y.a, 1, 0)
`CHECK(s.y.b, 1, 1)
- // TODO(zachjs): support access to whole sub-structs and unions
- // `CHECK(s.x, 2, 0)
- // `CHECK(s.y, 2, 1)
+ `CHECK(s.x, 2, 0)
+ `CHECK(s.y, 2, 1)
assert (fail === 0);
end