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-rw-r--r--tests/aiger/neg.ys36
-rwxr-xr-xtests/aiger/run-test.sh5
-rw-r--r--tests/arch/intel_alm/lutram.ys20
-rw-r--r--tests/opt/bug2010.ys10
-rw-r--r--tests/opt/opt_clean_init.ys13
-rw-r--r--tests/simple/partsel.v46
-rw-r--r--tests/various/bug2014.ys12
-rw-r--r--tests/various/gen_if_null.v13
-rw-r--r--tests/various/gen_if_null.ys4
-rw-r--r--tests/various/primitives.ys16
-rw-r--r--tests/various/specify.ys6
-rw-r--r--tests/verilog/.gitignore3
-rw-r--r--tests/verilog/bug2042-sv.ys59
-rw-r--r--tests/verilog/bug2042.ys11
-rwxr-xr-xtests/verilog/run-test.sh20
-rw-r--r--tests/verilog/upto.ys4
16 files changed, 278 insertions, 0 deletions
diff --git a/tests/aiger/neg.ys b/tests/aiger/neg.ys
new file mode 100644
index 000000000..4c1edd8a4
--- /dev/null
+++ b/tests/aiger/neg.ys
@@ -0,0 +1,36 @@
+read_verilog <<EOT
+module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
+assign c = a & b;
+endmodule
+EOT
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+design -save read
+
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_aiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+
+
+design -load read
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_xaiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 8e932b091..de7bc68cf 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -52,3 +52,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 16 miter
" -l ${aig}.log
done
+
+for y in *.ys; do
+ echo "Running $y."
+ ../../yosys $y -ql ${y%.*}.log
+done
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
new file mode 100644
index 000000000..6f997b67b
--- /dev/null
+++ b/tests/arch/intel_alm/lutram.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 16 t:MISTRAL_MLAB
+select -assert-count 1 t:MISTRAL_NOT
+select -assert-count 2 t:MISTRAL_ALUT2
+select -assert-count 8 t:MISTRAL_ALUT3
+select -assert-count 17 t:MISTRAL_FF
+select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+
diff --git a/tests/opt/bug2010.ys b/tests/opt/bug2010.ys
new file mode 100644
index 000000000..cef820867
--- /dev/null
+++ b/tests/opt/bug2010.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module test (
+ input signed [1:0] n,
+ output [3:0] dout
+);
+ assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+equiv_opt -assert opt -fine
diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys
new file mode 100644
index 000000000..0d567608d
--- /dev/null
+++ b/tests/opt/opt_clean_init.ys
@@ -0,0 +1,13 @@
+logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
+logger -expect-no-warnings
+read_verilog <<EOT
+module top;
+(* init=1'b0 *) wire w = 1'b0;
+(* init=1'bx *) wire x = 1'b0;
+(* init=1'b1 *) wire y = 1'b0;
+(* init=1'b0 *) wire z = 1'bx;
+endmodule
+EOT
+clean
+select -assert-count 1 a:init
+select -assert-count 1 w:y a:init %i
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 83493fcb0..5e9730d6b 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -64,3 +64,49 @@ endmodule
module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
assign dout = din[a*b +: 2];
endmodule
+
+module partsel_test004 (
+ input [31:0] din,
+ input signed [4:0] n,
+ output reg [31:0] dout
+);
+ always @(*) begin
+ dout = 0;
+ dout[n+1 +: 2] = din[n +: 2];
+ end
+endmodule
+
+
+module partsel_test005 (
+ input [31:0] din,
+ input signed [4:0] n,
+ output reg [31:0] dout
+);
+ always @(*) begin
+ dout = 0;
+ dout[n+1] = din[n];
+ end
+endmodule
+
+module partsel_test006 (
+ input [31:-32] din,
+ input signed [4:0] n,
+ output reg [31:-32] dout
+);
+ always @(*) begin
+ dout = 0;
+ dout[n+1 +: 2] = din[n +: 2];
+ end
+endmodule
+
+
+module partsel_test007 (
+ input [31:-32] din,
+ input signed [4:0] n,
+ output reg [31:-32] dout
+);
+ always @(*) begin
+ dout = 0;
+ dout[n+1] = din[n];
+ end
+endmodule
diff --git a/tests/various/bug2014.ys b/tests/various/bug2014.ys
new file mode 100644
index 000000000..10131fc43
--- /dev/null
+++ b/tests/various/bug2014.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module test (
+ input signed [1:0] n,
+ output [3:0] dout
+);
+ assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+equiv_opt -assert opt -fine
diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v
new file mode 100644
index 000000000..a12ac6288
--- /dev/null
+++ b/tests/various/gen_if_null.v
@@ -0,0 +1,13 @@
+module test(x, y, z);
+ localparam OFF = 0;
+ generate
+ if (OFF) ;
+ else input x;
+ if (!OFF) input y;
+ else ;
+ if (OFF) ;
+ else ;
+ if (OFF) ;
+ input z;
+ endgenerate
+endmodule
diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys
new file mode 100644
index 000000000..31dfc444b
--- /dev/null
+++ b/tests/various/gen_if_null.ys
@@ -0,0 +1,4 @@
+read_verilog gen_if_null.v
+select -assert-count 1 test/x
+select -assert-count 1 test/y
+select -assert-count 1 test/z
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys
new file mode 100644
index 000000000..9307ca50f
--- /dev/null
+++ b/tests/various/primitives.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input a, b, output [5:0] y);
+and (y[0], a, b);
+nand (y[1], a, b);
+or (y[2], a, b);
+nor (y[3], a, b);
+xor (y[4], a, b);
+xnor (y[5], a, b);
+endmodule
+EOT
+select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 9d55b8eb5..d7260d524 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -4,10 +4,16 @@ cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
+select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
+select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
+select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
cd test2
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
+select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
+ # ^^ Note use of macro
+select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
cd
write_verilog specify.out
design -stash gold
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/verilog/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
new file mode 100644
index 000000000..e815d7fc5
--- /dev/null
+++ b/tests/verilog/bug2042-sv.ys
@@ -0,0 +1,59 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+ task SomeTaskName(a);
+ b = ~a;
+ endtask
+
+ always @*
+ SomeTaskName(a);
+
+ assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b, c
+);
+
+ task SomeTaskName(x, output y, z);
+ y = ~x;
+ z = x;
+ endtask
+
+ always @*
+ SomeTaskName(a, b, c);
+
+ assert property (b == ~a);
+ assert property (c == a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+ task SomeTaskName(a)
+ endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
new file mode 100644
index 000000000..f9d8e2837
--- /dev/null
+++ b/tests/verilog/bug2042.ys
@@ -0,0 +1,11 @@
+logger -expect error "task/function argument direction missing" 1
+read_verilog <<EOT
+module Task_Test_Top
+(
+);
+
+ task SomeTaskName(a)
+ endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/verilog/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
new file mode 100644
index 000000000..2f3394761
--- /dev/null
+++ b/tests/verilog/upto.ys
@@ -0,0 +1,4 @@
+read_verilog <<EOT
+module top(input [-128:-65] a);
+endmodule
+EOT
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 22:06:01 +0000