aboutsummaryrefslogtreecommitdiffstats
path: root/tests
diff options
context:
space:
mode:
Diffstat (limited to 'tests')
-rw-r--r--tests/opt/opt_expr_combined_assign.ys83
-rw-r--r--tests/svtypes/static_cast_negative.ys4
-rw-r--r--tests/svtypes/static_cast_nonconst.ys4
-rw-r--r--tests/svtypes/static_cast_simple.sv64
-rw-r--r--tests/svtypes/static_cast_verilog.ys4
-rw-r--r--tests/svtypes/static_cast_zero.ys4
-rw-r--r--tests/various/const_func.v75
-rw-r--r--tests/various/const_func.ys1
8 files changed, 239 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
new file mode 100644
index 000000000..b18923c7b
--- /dev/null
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -0,0 +1,83 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a |= i;
+ a |= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a += i;
+ a += j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a ^= i;
+ a ^= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a -= i;
+ a -= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b11111111;
+initial begin
+ a &= i;
+ a &= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/svtypes/static_cast_negative.ys b/tests/svtypes/static_cast_negative.ys
new file mode 100644
index 000000000..4f9e8cf6e
--- /dev/null
+++ b/tests/svtypes/static_cast_negative.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with zero or negative size" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a = (-1)'(a); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_nonconst.ys b/tests/svtypes/static_cast_nonconst.ys
new file mode 100644
index 000000000..72d8f9910
--- /dev/null
+++ b/tests/svtypes/static_cast_nonconst.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with non constant expression" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a, b = (a)'(0); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_simple.sv b/tests/svtypes/static_cast_simple.sv
new file mode 100644
index 000000000..2e4ad7d2b
--- /dev/null
+++ b/tests/svtypes/static_cast_simple.sv
@@ -0,0 +1,64 @@
+module top;
+ wire [7:0] a, b, c, d;
+ assign a = 8'd16;
+ assign b = 8'd16;
+ assign c = (a * b) >> 8;
+ assign d = (16'(a) * b) >> 8;
+
+ parameter P = 16;
+
+ wire signed [7:0] s0, s1, s2;
+ wire [7:0] u0, u1, u2, u3, u4, u5, u6;
+ assign s0 = -8'd1;
+ assign s1 = 4'(s0);
+ assign s2 = 4'(unsigned'(s0));
+ assign u0 = -8'd1;
+ assign u1 = 4'(u0);
+ assign u2 = 4'(signed'(u0));
+ assign u3 = 8'(4'(s0));
+ assign u4 = 8'(4'(u0));
+ assign u5 = 8'(4'(signed'(-8'd1)));
+ assign u6 = 8'(4'(unsigned'(-8'd1)));
+
+ wire [8:0] n0, n1, n2, n3, n4, n5, n6, n7, n8, n9;
+ assign n0 = s1;
+ assign n1 = s2;
+ assign n2 = 9'(s1);
+ assign n3 = 9'(s2);
+ assign n4 = 9'(unsigned'(s1));
+ assign n5 = 9'(unsigned'(s2));
+ assign n6 = 9'(u0);
+ assign n7 = 9'(u1);
+ assign n8 = 9'(signed'(u0));
+ assign n9 = 9'(signed'(u1));
+
+ always_comb begin
+ assert(c == 8'b0000_0000);
+ assert(d == 8'b0000_0001);
+
+ assert((P + 1)'(a) == 17'b0_0000_0000_0001_0000);
+ assert((P + 1)'(d - 2) == 17'b1_1111_1111_1111_1111);
+
+ assert(s0 == 8'b1111_1111);
+ assert(s1 == 8'b1111_1111);
+ assert(s2 == 8'b0000_1111);
+ assert(u0 == 8'b1111_1111);
+ assert(u1 == 8'b0000_1111);
+ assert(u2 == 8'b1111_1111);
+ assert(u3 == 8'b1111_1111);
+ assert(u4 == 8'b0000_1111);
+ assert(u5 == 8'b1111_1111);
+ assert(u6 == 8'b0000_1111);
+
+ assert(n0 == 9'b1_1111_1111);
+ assert(n1 == 9'b0_0000_1111);
+ assert(n2 == 9'b1_1111_1111);
+ assert(n3 == 9'b0_0000_1111);
+ assert(n4 == 9'b0_1111_1111);
+ assert(n5 == 9'b0_0000_1111);
+ assert(n6 == 9'b0_1111_1111);
+ assert(n7 == 9'b0_0000_1111);
+ assert(n8 == 9'b1_1111_1111);
+ assert(n9 == 9'b0_0000_1111);
+ end
+endmodule
diff --git a/tests/svtypes/static_cast_verilog.ys b/tests/svtypes/static_cast_verilog.ys
new file mode 100644
index 000000000..fa3680b68
--- /dev/null
+++ b/tests/svtypes/static_cast_verilog.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast is only supported in SystemVerilog mode" 1
+read_verilog <<EOT
+module top; wire [7:0] a = 1'(a); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_zero.ys b/tests/svtypes/static_cast_zero.ys
new file mode 100644
index 000000000..d8335ca1b
--- /dev/null
+++ b/tests/svtypes/static_cast_zero.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with zero or negative size" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a = 0'(a); endmodule
+EOT
diff --git a/tests/various/const_func.v b/tests/various/const_func.v
new file mode 100644
index 000000000..76cdc385d
--- /dev/null
+++ b/tests/various/const_func.v
@@ -0,0 +1,75 @@
+module Example(outA, outB, outC, outD);
+ parameter OUTPUT = "FOO";
+ output wire [23:0] outA;
+ output wire [23:0] outB;
+ output reg outC, outD;
+ function automatic [23:0] flip;
+ input [23:0] inp;
+ flip = ~inp;
+ endfunction
+
+ generate
+ if (flip(OUTPUT) == flip("BAR"))
+ assign outA = OUTPUT;
+ else
+ assign outA = 0;
+
+ case (flip(OUTPUT))
+ flip("FOO"): assign outB = OUTPUT;
+ flip("BAR"): assign outB = 0;
+ flip("BAZ"): assign outB = "HI";
+ endcase
+
+ genvar i;
+ initial outC = 0;
+ for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
+ if (i + 1 == flip(flip("O")))
+ initial outC = 1;
+ endgenerate
+
+ integer j;
+ initial begin
+ outD = 1;
+ for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
+ if (j + 1 == flip(flip("O")))
+ outD = 0;
+ end
+endmodule
+
+module top(out);
+ wire [23:0] a1, a2, a3, a4;
+ wire [23:0] b1, b2, b3, b4;
+ wire c1, c2, c3, c4;
+ wire d1, d2, d3, d4;
+ Example e1(a1, b1, c1, d1);
+ Example #("FOO") e2(a2, b2, c2, d2);
+ Example #("BAR") e3(a3, b3, c3, d3);
+ Example #("BAZ") e4(a4, b4, c4, d4);
+
+ output wire [24 * 8 - 1 + 4 :0] out;
+ assign out = {
+ a1, a2, a3, a4,
+ b1, b2, b3, b4,
+ c1, c2, c3, c4,
+ d1, d2, d3, d4};
+
+// `define VERIFY
+`ifdef VERIFY
+ assert property (a1 == 0);
+ assert property (a2 == 0);
+ assert property (a3 == "BAR");
+ assert property (a4 == 0);
+ assert property (b1 == "FOO");
+ assert property (b2 == "FOO");
+ assert property (b3 == 0);
+ assert property (b4 == "HI");
+ assert property (c1 == 1);
+ assert property (c2 == 1);
+ assert property (c3 == 0);
+ assert property (c4 == 0);
+ assert property (d1 == 0);
+ assert property (d2 == 0);
+ assert property (d3 == 1);
+ assert property (d4 == 1);
+`endif
+endmodule
diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys
new file mode 100644
index 000000000..5e3c04105
--- /dev/null
+++ b/tests/various/const_func.ys
@@ -0,0 +1 @@
+read_verilog const_func.v
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 15:13:17 +0000