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-rw-r--r--tests/simple_abc9/abc.box2
-rw-r--r--tests/simple_abc9/abc9.v217
-rwxr-xr-xtests/simple_abc9/run-test.sh22
-rwxr-xr-xtests/tools/autotest.sh2
-rw-r--r--tests/various/split_shiftx.v118
-rw-r--r--tests/various/split_shiftx.ys21
6 files changed, 381 insertions, 1 deletions
diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box
new file mode 100644
index 000000000..a8801d807
--- /dev/null
+++ b/tests/simple_abc9/abc.box
@@ -0,0 +1,2 @@
+MUXF8 1 0 3 1
+1 1 1
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
new file mode 100644
index 000000000..fb5b759fb
--- /dev/null
+++ b/tests/simple_abc9/abc9.v
@@ -0,0 +1,217 @@
+module abc9_test001(input a, output o);
+assign o = a;
+endmodule
+
+module abc9_test002(input [1:0] a, output o);
+assign o = a[1];
+endmodule
+
+module abc9_test003(input [1:0] a, output [1:0] o);
+assign o = a;
+endmodule
+
+module abc9_test004(input [1:0] a, output o);
+assign o = ^a;
+endmodule
+
+module abc9_test005(input [1:0] a, output o, output p);
+assign o = ^a;
+assign p = ~o;
+endmodule
+
+module abc9_test006(input [1:0] a, output [2:0] o);
+assign o[0] = ^a;
+assign o[1] = ~o[0];
+assign o[2] = o[1];
+endmodule
+
+module abc9_test007(input a, output o);
+wire b, c;
+assign c = ~a;
+assign b = c;
+abc9_test007_sub s(b, o);
+endmodule
+
+module abc9_test007_sub(input a, output b);
+assign b = a;
+endmodule
+
+module abc9_test008(input a, output o);
+wire b, c;
+assign b = ~a;
+assign c = b;
+abc9_test008_sub s(b, o);
+endmodule
+
+module abc9_test008_sub(input a, output b);
+assign b = ~a;
+endmodule
+
+module abc9_test009(inout io, input oe);
+reg latch;
+always @(io or oe)
+ if (!oe)
+ latch <= io;
+assign io = oe ? ~latch : 1'bz;
+endmodule
+
+module abc9_test010(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+ if (!oe)
+ latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test011(inout io, input oe);
+reg latch;
+always @(io or oe)
+ if (!oe)
+ latch <= io;
+//assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test012(inout io, input oe);
+reg latch;
+//always @(io or oe)
+// if (!oe)
+// latch <= io;
+assign io = oe ? ~latch : 8'bz;
+endmodule
+
+module abc9_test013(inout [3:0] io, input oe);
+reg [3:0] latch;
+always @(io or oe)
+ if (!oe)
+ latch[3:0] <= io[3:0];
+ else
+ latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule
+
+module abc9_test014(inout [7:0] io, input oe);
+abc9_test012_sub sub(io, oe);
+endmodule
+
+module abc9_test012_sub(inout [7:0] io, input oe);
+reg [7:0] latch;
+always @(io or oe)
+ if (!oe)
+ latch[3:0] <= io;
+ else
+ latch[7:4] <= io;
+assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
+assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
+endmodule
+
+module abc9_test015(input a, output b, input c);
+assign b = ~a;
+(* keep *) wire d;
+assign d = ~c;
+endmodule
+
+module abc9_test016(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c <= ~a;
+endmodule
+
+module abc9_test017(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c = b;
+endmodule
+
+module abc9_test018(input a, output b, output c);
+assign b = ~a;
+(* keep *) wire [1:0] d;
+assign c = &d;
+endmodule
+
+module abc9_test019(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+reg d;
+always @* d <= &c;
+endmodule
+
+module abc9_test020(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+(* keep *) reg d;
+always @* d <= &c;
+endmodule
+
+module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
+ input clk;
+ output [47:0] m_eth_dest_mac;
+ input m_eth_hdr_ready;
+ output m_eth_hdr_valid;
+ output [7:0] m_eth_payload_axis_tdata;
+ output [7:0] m_eth_payload_axis_tdest;
+ output [7:0] m_eth_payload_axis_tid;
+ output m_eth_payload_axis_tkeep;
+ output m_eth_payload_axis_tlast;
+ input m_eth_payload_axis_tready;
+ output m_eth_payload_axis_tuser;
+ output m_eth_payload_axis_tvalid;
+ output [47:0] m_eth_src_mac;
+ output [15:0] m_eth_type;
+ input rst;
+ input [191:0] s_eth_dest_mac;
+ output [3:0] s_eth_hdr_ready;
+ input [3:0] s_eth_hdr_valid;
+ input [31:0] s_eth_payload_axis_tdata;
+ input [31:0] s_eth_payload_axis_tdest;
+ input [31:0] s_eth_payload_axis_tid;
+ input [3:0] s_eth_payload_axis_tkeep;
+ input [3:0] s_eth_payload_axis_tlast;
+ output [3:0] s_eth_payload_axis_tready;
+ input [3:0] s_eth_payload_axis_tuser;
+ input [3:0] s_eth_payload_axis_tvalid;
+ input [191:0] s_eth_src_mac;
+ input [63:0] s_eth_type;
+ (* keep *)
+ wire [0:0] grant, request;
+ wire a;
+ not u0 (
+ a,
+ grant[0]
+ );
+ and u1 (
+ request[0],
+ s_eth_hdr_valid[0],
+ a
+ );
+ (* keep *)
+ MUXF8 u2 (
+ .I0(1'bx),
+ .I1(1'bx),
+ .O(o),
+ .S(1'bx)
+ );
+ arbiter arb_inst (
+ .acknowledge(acknowledge),
+ .clk(clk),
+ .grant(grant),
+ .grant_encoded(grant_encoded),
+ .grant_valid(grant_valid),
+ .request(request),
+ .rst(rst)
+ );
+endmodule
+
+module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
+ input [3:0] acknowledge;
+ input clk;
+ output [3:0] grant;
+ output [1:0] grant_encoded;
+ output grant_valid;
+ input [3:0] request;
+ input rst;
+endmodule
+
+(* abc_box_id=1 *)
+module MUXF8(input I0, I1, S, output O);
+endmodule
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
new file mode 100755
index 000000000..4935d41ad
--- /dev/null
+++ b/tests/simple_abc9/run-test.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+
+OPTIND=1
+seed="" # default to no seed specified
+while getopts "S:" opt
+do
+ case "$opt" in
+ S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+ seed="SEED=$arg" ;;
+ esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+ echo "$0: Error: Icarus Verilog 'iverilog' not found."
+ exit 1
+fi
+
+cp ../simple/*.v .
+DOLLAR='?'
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index bb9c3bfb5..86a90793e 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -132,13 +132,13 @@ do
fn=$(basename $fn)
bn=$(basename $bn)
- rm -f ${bn}_ref.fir
if [[ "$ext" == "v" ]]; then
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog -noblackbox"
fi
+ rm -f ${bn}_ref.fir
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v
new file mode 100644
index 000000000..dfcea3880
--- /dev/null
+++ b/tests/various/split_shiftx.v
@@ -0,0 +1,118 @@
+module split_shiftx_test01(i, s, o);
+ wire [3:0] _0_;
+ input [8:0] i;
+ output [2:0] o;
+ input [1:0] s;
+ \$macc #(
+ .A_WIDTH(32'd4),
+ .B_WIDTH(32'd0),
+ .CONFIG(10'h282),
+ .CONFIG_WIDTH(32'd10),
+ .Y_WIDTH(32'd4)
+ ) _1_ (
+ .A({ 2'h3, s }),
+ .B(),
+ .Y(_0_)
+ );
+ \$shiftx #(
+ .A_SIGNED(32'd0),
+ .A_WIDTH(32'd9),
+ .B_SIGNED(32'd1),
+ .B_WIDTH(32'd5),
+ .Y_WIDTH(32'd3)
+ ) _2_ (
+ .A(i),
+ .B({ 1'h0, _0_ }),
+ .Y(o)
+ );
+endmodule
+
+// Sign bit is 1
+module split_shiftx_test02(i, s, o);
+ wire [3:0] _0_;
+ input [8:0] i;
+ output [2:0] o;
+ input [1:0] s;
+ \$macc #(
+ .A_WIDTH(32'd4),
+ .B_WIDTH(32'd0),
+ .CONFIG(10'h282),
+ .CONFIG_WIDTH(32'd10),
+ .Y_WIDTH(32'd4)
+ ) _1_ (
+ .A({ 2'h3, s }),
+ .B(),
+ .Y(_0_)
+ );
+ \$shiftx #(
+ .A_SIGNED(32'd0),
+ .A_WIDTH(32'd9),
+ .B_SIGNED(32'd1),
+ .B_WIDTH(32'd5),
+ .Y_WIDTH(32'd3)
+ ) _2_ (
+ .A(i),
+ .B({ 1'h1, _0_ }),
+ .Y(o)
+ );
+endmodule
+
+// Non constant $macc
+module split_shiftx_test03(i, s, o);
+ wire [3:0] _0_;
+ input [8:0] i;
+ output [2:0] o;
+ input [1:0] s;
+ \$macc #(
+ .A_WIDTH(32'd4),
+ .B_WIDTH(32'd0),
+ .CONFIG(10'h282),
+ .CONFIG_WIDTH(32'd10),
+ .Y_WIDTH(32'd4)
+ ) _1_ (
+ .A({ s, s }),
+ .B(),
+ .Y(_0_)
+ );
+ \$shiftx #(
+ .A_SIGNED(32'd0),
+ .A_WIDTH(32'd9),
+ .B_SIGNED(32'd1),
+ .B_WIDTH(32'd5),
+ .Y_WIDTH(32'd3)
+ ) _2_ (
+ .A(i),
+ .B({ 1'h0, _0_ }),
+ .Y(o)
+ );
+endmodule
+
+// Wrong constant $macc
+module split_shiftx_test04(i, s, o);
+ wire [3:0] _0_;
+ input [8:0] i;
+ output [2:0] o;
+ input [1:0] s;
+ \$macc #(
+ .A_WIDTH(32'd4),
+ .B_WIDTH(32'd0),
+ .CONFIG(10'h282),
+ .CONFIG_WIDTH(32'd10),
+ .Y_WIDTH(32'd4)
+ ) _1_ (
+ .A({ 2'h2, s }),
+ .B(),
+ .Y(_0_)
+ );
+ \$shiftx #(
+ .A_SIGNED(32'd0),
+ .A_WIDTH(32'd9),
+ .B_SIGNED(32'd1),
+ .B_WIDTH(32'd5),
+ .Y_WIDTH(32'd3)
+ ) _2_ (
+ .A(i),
+ .B({ 1'h0, _0_ }),
+ .Y(o)
+ );
+endmodule
diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys
new file mode 100644
index 000000000..810348aa3
--- /dev/null
+++ b/tests/various/split_shiftx.ys
@@ -0,0 +1,21 @@
+read_verilog -icells split_shiftx.v
+split_shiftx
+
+cd split_shiftx_test01
+select -assert-count 3 t:$shiftx
+select -assert-count 0 t: t:$shiftx %n %i
+
+cd split_shiftx_test02
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test03
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
+
+cd split_shiftx_test04
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$macc
+select -assert-count 0 t: t:$shiftx t:$macc %u %n %i
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