10 files changed, 134 insertions, 0 deletions
diff --git a/tests/verilog/conflict_assert.ys b/tests/verilog/conflict_assert.ys
new file mode 100644
index 000000000..121a0cf51
--- /dev/null
+++ b/tests/verilog/conflict_assert.ys
@@ -0,0 +1,8 @@
+logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1
+read_verilog -sv <<EOT
+module top;
+    wire x, y;
+    always @*
+        x: assert(y == 1);
+endmodule
+EOT
diff --git a/tests/verilog/conflict_cell_memory.ys b/tests/verilog/conflict_cell_memory.ys
new file mode 100644
index 000000000..ddc67596f
--- /dev/null
+++ b/tests/verilog/conflict_cell_memory.ys
@@ -0,0 +1,9 @@
+logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1
+read_verilog <<EOT
+module mod;
+endmodule
+module top;
+    reg [2:0] x [0:0];
+    mod x();
+endmodule
+EOT
diff --git a/tests/verilog/conflict_interface_port.ys b/tests/verilog/conflict_interface_port.ys
new file mode 100644
index 000000000..b97ec029e
--- /dev/null
+++ b/tests/verilog/conflict_interface_port.ys
@@ -0,0 +1,17 @@
+logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
+read_verilog -sv <<EOT
+interface intf;
+    logic x;
+    assign x = 1;
+    modport m(input x);
+endinterface
+module mod(intf.m i);
+    wire x;
+    assign x = i.x;
+    wire i;
+endmodule
+module top;
+    intf i();
+    mod m(i);
+endmodule
+EOT
diff --git a/tests/verilog/conflict_memory_wire.ys b/tests/verilog/conflict_memory_wire.ys
new file mode 100644
index 000000000..5c296074f
--- /dev/null
+++ b/tests/verilog/conflict_memory_wire.ys
@@ -0,0 +1,7 @@
+logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1
+read_verilog <<EOT
+module top;
+    reg [2:0] x;
+    reg [2:0] x [0:0];
+endmodule
+EOT
diff --git a/tests/verilog/conflict_pwire.ys b/tests/verilog/conflict_pwire.ys
new file mode 100644
index 000000000..ecc30d33a
--- /dev/null
+++ b/tests/verilog/conflict_pwire.ys
@@ -0,0 +1,8 @@
+logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
+read_verilog -pwires <<EOT
+module top;
+    wire x;
+    assign x = 1;
+    localparam x = 2;
+endmodule
+EOT
diff --git a/tests/verilog/conflict_wire_memory.ys b/tests/verilog/conflict_wire_memory.ys
new file mode 100644
index 000000000..77520fea9
--- /dev/null
+++ b/tests/verilog/conflict_wire_memory.ys
@@ -0,0 +1,7 @@
+logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
+read_verilog <<EOT
+module top;
+    reg [2:0] x [0:0];
+    reg [2:0] x;
+endmodule
+EOT
diff --git a/tests/verilog/int_types.sv b/tests/verilog/int_types.sv
new file mode 100644
index 000000000..8133f8218
--- /dev/null
+++ b/tests/verilog/int_types.sv
@@ -0,0 +1,47 @@
+`define TEST(typ, width, is_signed) \
+    if (1) begin \
+        typ x = -1; \
+        localparam typ y = -1; \
+        logic [127:0] a = x; \
+        logic [127:0] b = y; \
+        if ($bits(x) != width) \
+            $error(`"typ doesn't have expected size width`"); \
+        if ($bits(x) != $bits(y)) \
+            $error(`"localparam typ doesn't match size of typ`"); \
+        function automatic typ f; \
+            input integer x; \
+            f = x; \
+        endfunction \
+        logic [127:0] c = f(-1); \
+        always @* begin \
+            assert (x == y); \
+            assert (a == b); \
+            assert (a == c); \
+            assert ((a == -1) == is_signed); \
+        end \
+    end
+
+`define TEST_INTEGER_ATOM(typ, width) \
+    `TEST(typ, width, 1) \
+    `TEST(typ signed, width, 1) \
+    `TEST(typ unsigned, width, 0)
+
+`define TEST_INTEGER_VECTOR(typ) \
+    `TEST(typ, 1, 0) \
+    `TEST(typ signed, 1, 1) \
+    `TEST(typ unsigned, 1, 0) \
+    `TEST(typ [1:0], 2, 0) \
+    `TEST(typ signed [1:0], 2, 1) \
+    `TEST(typ unsigned [1:0], 2, 0)
+
+module top;
+    `TEST_INTEGER_ATOM(integer, 32)
+    `TEST_INTEGER_ATOM(int, 32)
+    `TEST_INTEGER_ATOM(shortint, 16)
+    `TEST_INTEGER_ATOM(longint, 64)
+    `TEST_INTEGER_ATOM(byte, 8)
+
+    `TEST_INTEGER_VECTOR(reg)
+    `TEST_INTEGER_VECTOR(logic)
+    `TEST_INTEGER_VECTOR(bit)
+endmodule
diff --git a/tests/verilog/int_types.ys b/tests/verilog/int_types.ys
new file mode 100644
index 000000000..c17c44b4c
--- /dev/null
+++ b/tests/verilog/int_types.ys
@@ -0,0 +1,7 @@
+read_verilog -sv int_types.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/param_int_types.sv b/tests/verilog/param_int_types.sv
new file mode 100644
index 000000000..3228369b8
--- /dev/null
+++ b/tests/verilog/param_int_types.sv
@@ -0,0 +1,19 @@
+module gate(out);
+    parameter integer a = -1;
+    parameter int b = -2;
+    parameter shortint c = -3;
+    parameter longint d = -4;
+    parameter byte e = -5;
+    output wire [1023:0] out;
+    assign out = {a, b, c, d, e};
+endmodule
+
+module gold(out);
+    integer a = -1;
+    int b = -2;
+    shortint c = -3;
+    longint d = -4;
+    byte e = -5;
+    output wire [1023:0] out;
+    assign out = {a, b, c, d, e};
+endmodule
diff --git a/tests/verilog/param_int_types.ys b/tests/verilog/param_int_types.ys
new file mode 100644
index 000000000..7727801cf
--- /dev/null
+++ b/tests/verilog/param_int_types.ys
@@ -0,0 +1,5 @@
+read_verilog -sv param_int_types.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert