3 files changed, 42 insertions, 0 deletions
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
new file mode 100644
index 000000000..15cab5121
--- /dev/null
+++ b/tests/various/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys
new file mode 100644
index 000000000..84faea08a
--- /dev/null
+++ b/tests/various/bug1480.ys
@@ -0,0 +1,18 @@
+read_verilog << EOF
+module top(...);
+
+input signed [17:0] A;
+input signed [17:0] B;
+output X;
+output Y;
+
+wire [35:0] P;
+assign P = A * B;
+
+assign X = P[0];
+assign Y = P[35];
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1496.ys b/tests/various/bug1496.ys
new file mode 100644
index 000000000..d050161dc
--- /dev/null
+++ b/tests/various/bug1496.ys
@@ -0,0 +1,13 @@
+read_ilang << EOF
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  cell $_AND_ \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+EOF
+
+extract_fa