diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/intel_alm/mul.ys | 23 | ||||
| -rw-r--r-- | tests/opt/bug2221.ys | 16 |
2 files changed, 39 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys new file mode 100644 index 000000000..92f00156a --- /dev/null +++ b/tests/arch/intel_alm/mul.ys @@ -0,0 +1,23 @@ +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +stat + +select -assert-count 1 t:MISTRAL_MUL9X9 +select -assert-none t:MISTRAL_MUL9X9 %% t:* %D + +design -reset +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18. +select -assert-count 1 t:MISTRAL_MUL18X18 +select -assert-none t:MISTRAL_MUL18X18 %% t:* %D diff --git a/tests/opt/bug2221.ys b/tests/opt/bug2221.ys new file mode 100644 index 000000000..8ac380243 --- /dev/null +++ b/tests/opt/bug2221.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module test ( + input [1:0] a, + input [1:0] b, + output [5:0] y +); + +wire [5:0] aa = {a, 4'h0}; +wire [5:0] bb = {b, 4'h0}; + +assign y = aa * bb; + +endmodule +EOT + +equiv_opt -assert opt_expr |