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-rw-r--r--tests/arch/common/mul.v7
-rw-r--r--tests/arch/intel_alm/mul.ys43
-rw-r--r--tests/simple/generate.v16
-rw-r--r--tests/techmap/bug2183.ys11
-rw-r--r--tests/various/const_arg_loop.v20
5 files changed, 91 insertions, 6 deletions
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v
index 437a91cfc..baed64fcd 100644
--- a/tests/arch/common/mul.v
+++ b/tests/arch/common/mul.v
@@ -1,9 +1,10 @@
module top
+#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12)
(
- input [5:0] x,
- input [5:0] y,
+ input [X_WIDTH-1:0] x,
+ input [Y_WIDTH-1:0] y,
- output [11:0] A,
+ output [A_WIDTH-1:0] A,
);
assign A = x * y;
endmodule
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys
index 92f00156a..49934740f 100644
--- a/tests/arch/intel_alm/mul.ys
+++ b/tests/arch/intel_alm/mul.ys
@@ -1,23 +1,60 @@
read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-stat
-
select -assert-count 1 t:MISTRAL_MUL9X9
select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
+# Cyclone 10 GX does not have 9x9 multipliers.
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
+hierarchy -top top
+proc
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:MISTRAL_MUL18X18
+select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
+
design -reset
read_verilog ../common/mul.v
+chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
hierarchy -top top
proc
equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18.
select -assert-count 1 t:MISTRAL_MUL18X18
select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
+hierarchy -top top
+proc
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:MISTRAL_MUL27X27
+select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
+hierarchy -top top
+proc
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:MISTRAL_MUL27X27
+select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index dcd450e47..12327b36e 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -223,6 +223,10 @@ module gen_test8;
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
+ `ASSERT(gen_test8.x == 3)
+ `ASSERT(gen_test8.A.x == 2)
+ `ASSERT(gen_test8.A.C.x == 1)
+ `ASSERT(gen_test8.A.B.x == 0)
end
begin : C
wire [1:0] x = 2'b01;
@@ -230,12 +234,20 @@ module gen_test8;
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
+ `ASSERT(gen_test8.x == 3)
+ `ASSERT(gen_test8.A.x == 2)
+ `ASSERT(gen_test8.A.C.x == 1)
+ `ASSERT(gen_test8.A.B.x == 0)
end
assign x = B.x ^ 2'b11 ^ C.x;
`ASSERT(x == 2)
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
+ `ASSERT(gen_test8.x == 3)
+ `ASSERT(gen_test8.A.x == 2)
+ `ASSERT(gen_test8.A.C.x == 1)
+ `ASSERT(gen_test8.A.B.x == 0)
end
endgenerate
@@ -243,4 +255,8 @@ module gen_test8;
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
+ `ASSERT(gen_test8.x == 3)
+ `ASSERT(gen_test8.A.x == 2)
+ `ASSERT(gen_test8.A.C.x == 1)
+ `ASSERT(gen_test8.A.B.x == 0)
endmodule
diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys
new file mode 100644
index 000000000..8dd09458e
--- /dev/null
+++ b/tests/techmap/bug2183.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module foo(inout a, b);
+ assign a = b;
+endmodule
+module bar(output c);
+ foo f(c, 1'b0);
+endmodule
+EOT
+
+hierarchy -auto-top
+flatten
diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
index 85318562f..3bfff4acd 100644
--- a/tests/various/const_arg_loop.v
+++ b/tests/various/const_arg_loop.v
@@ -23,6 +23,22 @@ module top;
end
endfunction
+ function automatic [31:0] operation3;
+ input [4:0] rounds;
+ input integer num;
+ reg [4:0] rounds;
+ integer i;
+ begin
+ begin : shadow
+ integer rounds;
+ rounds = 0;
+ end
+ for (i = 0; i < rounds; i = i + 1)
+ num = num * 2;
+ operation3 = num;
+ end
+ endfunction
+
wire [31:0] a;
assign a = 2;
@@ -34,11 +50,15 @@ module top;
wire [31:0] x2;
assign x2 = operation2(A, a);
+ wire [31:0] x3;
+ assign x3 = operation3(A, a);
+
// `define VERIFY
`ifdef VERIFY
assert property (a == 2);
assert property (A == 3);
assert property (x1 == 16);
assert property (x2 == 4);
+ assert property (x3 == 16);
`endif
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 17:15:31 +0000