diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/svtypes/typedef_struct.sv | 4 | ||||
| -rw-r--r-- | tests/svtypes/union_simple.sv | 16 | ||||
| -rw-r--r-- | tests/techmap/bmuxmap_pmux.ys | 45 |
3 files changed, 65 insertions, 0 deletions
diff --git a/tests/svtypes/typedef_struct.sv b/tests/svtypes/typedef_struct.sv index 7ae007952..8df8e32b0 100644 --- a/tests/svtypes/typedef_struct.sv +++ b/tests/svtypes/typedef_struct.sv @@ -16,6 +16,7 @@ module top; bit a; logic[7:0] b; t_t t; + p::p_t ps; } s_t; s_t s; @@ -29,6 +30,7 @@ module top; assign s1 = s; assign ps.a = 8'hAA; assign ps.b = 8'h55; + assign s.ps = ps; always_comb begin assert(s.a == 1'b1); @@ -37,6 +39,8 @@ module top; assert(s1.t == 8'h55); assert(ps.a == 8'hAA); assert(ps.b == 8'h55); + assert(s.ps.a == 8'hAA); + assert(s.ps.b == 8'h55); end endmodule diff --git a/tests/svtypes/union_simple.sv b/tests/svtypes/union_simple.sv index 12e4b376f..a55df4d0a 100644 --- a/tests/svtypes/union_simple.sv +++ b/tests/svtypes/union_simple.sv @@ -48,14 +48,30 @@ module top; U_t u; } instruction_t; + typedef struct packed { + instruction_t ir; + logic [3:0] state; + } s_t; + instruction_t ir1; + s_t s1; + assign ir1 = 32'h0AA01EB7; // lui t4,0xAA01 + assign s1.ir = ir1; + assign s1.state = '1; + always_comb begin assert(ir1.u.opcode == 'h37); assert(ir1.r.opcode == 'h37); assert(ir1.u.rd == 'd29); assert(ir1.r.rd == 'd29); assert(ir1.u.imm == 'hAA01); + assert(s1.ir.u.opcode == 'h37); + assert(s1.ir.r.opcode == 'h37); + assert(s1.ir.u.rd == 'd29); + assert(s1.ir.r.rd == 'd29); + assert(s1.ir.u.imm == 'hAA01); + assert(s1.state == 4'b1111); end union packed { diff --git a/tests/techmap/bmuxmap_pmux.ys b/tests/techmap/bmuxmap_pmux.ys new file mode 100644 index 000000000..c75d981e7 --- /dev/null +++ b/tests/techmap/bmuxmap_pmux.ys @@ -0,0 +1,45 @@ +read_ilang << EOT + +module \top + wire width 4 input 0 \S + wire width 5 output 1 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 4 + connect \A 80'10110100011101110001110010001110101010111000110011111111111110100000110100111000 + connect \S \S + connect \Y \Y + end +end + +EOT + +hierarchy -auto-top +equiv_opt -assert bmuxmap -pmux + +### +design -reset + +read_ilang << EOT + +module \top + wire width 10 input 0 \A + wire input 1 \S + wire width 5 output 2 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 1 + connect \A \A + connect \S \S + connect \Y \Y + end +end + +EOT + +hierarchy -auto-top +equiv_opt -assert bmuxmap -pmux + + |