diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/k68_vltor/changes.diff | 12 | ||||
| -rw-r--r-- | tests/k68_vltor/clone.sh | 6 | ||||
| -rw-r--r-- | tests/k68_vltor/run.sh | 30 | ||||
| -rw-r--r-- | tests/simple/always01.v | 10 | ||||
| -rw-r--r-- | tests/simple/always02.v | 13 | ||||
| -rw-r--r-- | tests/simple/always03.v | 22 | ||||
| -rw-r--r-- | tests/simple/arrays01.v | 16 | ||||
| -rw-r--r-- | tests/simple/forgen01.v | 20 | ||||
| -rw-r--r-- | tests/simple/forgen02.v | 30 | ||||
| -rw-r--r-- | tests/simple/process.v | 19 | ||||
| -rwxr-xr-x | tests/tools/vcdcd.pl | 20 |
11 files changed, 194 insertions, 4 deletions
diff --git a/tests/k68_vltor/changes.diff b/tests/k68_vltor/changes.diff new file mode 100644 index 000000000..7b9034032 --- /dev/null +++ b/tests/k68_vltor/changes.diff @@ -0,0 +1,12 @@ +diff --git a/bench/bench.cpp b/bench/bench.cpp +index 47a50c4..de27fbb 100755 +--- a/bench/bench.cpp ++++ b/bench/bench.cpp +@@ -71,6 +71,7 @@ int main(int argc, char **argv, char **env) { + main_time++; + top->arbclk_i = !top->arbclk_i; + if (main_time%5 == 0) top->clk = !top->clk; ++ if (main_time%100000 == 0) cout<<"Partial sum = "<<hex<<top->sum<<"\n"; + } + + cout<<"Final sum = "<<hex<<top->sum<<"\n"; diff --git a/tests/k68_vltor/clone.sh b/tests/k68_vltor/clone.sh new file mode 100644 index 000000000..54bba5219 --- /dev/null +++ b/tests/k68_vltor/clone.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -ex +rm -rf verilog-sim-benchmarks +git clone http://git.veripool.org/git/verilog-sim-benchmarks +cd verilog-sim-benchmarks +patch -p1 < ../changes.diff diff --git a/tests/k68_vltor/run.sh b/tests/k68_vltor/run.sh new file mode 100644 index 000000000..97ccf2389 --- /dev/null +++ b/tests/k68_vltor/run.sh @@ -0,0 +1,30 @@ +#!/bin/bash + +if ( + set -ex + cd verilog-sim-benchmarks + rm -rf obj_dir_* synth + + cd rtl + mkdir -p ../synth + ../../../../yosys -o ../synth/k68_soc.v -p 'hierarchy -check -top k68_soc; proc; opt; memory; opt' \ + k68_soc.v k68_arb.v k68_cpu.v k68_load.v k68_clkgen.v k68_decode.v k68_execute.v \ + k68_fetch.v k68_regbank.v k68_buni.v k68_b2d.v k68_ccc.v k68_d2b.v k68_rox.v \ + k68_calc.v k68_dpmem.v k68_sasc.v sasc_brg.v sasc_top.v sasc_fifo4.v + + cd .. + VERILATOR_OPT="-Wno-fatal -Ibench --cc bench/k68_soc_test.v --exe bench/bench.cpp -prefix m68 -x-assign 0" + verilator -Mdir obj_dir_rtl -Irtl $VERILATOR_OPT; make -C obj_dir_rtl -f m68.mk + verilator -Mdir obj_dir_synth -Isynth $VERILATOR_OPT; make -C obj_dir_synth -f m68.mk + + ./obj_dir_rtl/m68 100000 | tee output_rtl.txt + ./obj_dir_synth/m68 100000 | tee output_synth.txt + diff -u <( grep ' sum ' output_rtl.txt; ) <( grep ' sum ' output_synth.txt; ) +); then + echo OK + exit 0 +else + echo ERROR + exit 1 +fi + diff --git a/tests/simple/always01.v b/tests/simple/always01.v new file mode 100644 index 000000000..21379cb01 --- /dev/null +++ b/tests/simple/always01.v @@ -0,0 +1,10 @@ +module uut_always01(clock, reset, count); + +input clock, reset; +output [3:0] count; +reg [3:0] count; + +always @(posedge clock) + count <= reset ? 0 : count + 1; + +endmodule diff --git a/tests/simple/always02.v b/tests/simple/always02.v new file mode 100644 index 000000000..8c7ef0fb5 --- /dev/null +++ b/tests/simple/always02.v @@ -0,0 +1,13 @@ +module uut_always02(clock, reset, count); + +input clock, reset; +output [3:0] count; +reg [3:0] count; + +always @(posedge clock) begin + count <= count + 1; + if (reset) + count <= 0; +end + +endmodule diff --git a/tests/simple/always03.v b/tests/simple/always03.v new file mode 100644 index 000000000..5542175e5 --- /dev/null +++ b/tests/simple/always03.v @@ -0,0 +1,22 @@ +module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3); + +input clock, in1, in2, in3, in4, in5, in6, in7; +output out1, out2, out3; +reg out1, out2, out3; + +always @(posedge clock) begin + out1 = in1; + if (in2) + out1 = !out1; + out2 <= out1; + if (in3) + out2 <= out2; + if (in4) + if (in5) + out3 <= in6; + else + out3 <= in7; + out1 = out1 ^ out2; +end + +endmodule diff --git a/tests/simple/arrays01.v b/tests/simple/arrays01.v new file mode 100644 index 000000000..bd0eda294 --- /dev/null +++ b/tests/simple/arrays01.v @@ -0,0 +1,16 @@ +module uut_arrays01(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [15:0]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v new file mode 100644 index 000000000..70ee7e667 --- /dev/null +++ b/tests/simple/forgen01.v @@ -0,0 +1,20 @@ +module uut_forgen01(a, y); + +input [4:0] a; +output y; + +integer i, j; +reg [31:0] lut; + +initial begin + for (i = 0; i < 32; i = i+1) begin + lut[i] = i > 1; + for (j = 2; j*j <= i; j = j+1) + if (i % j == 0) + lut[i] = 0; + end +end + +assign y = lut[a]; + +endmodule diff --git a/tests/simple/forgen02.v b/tests/simple/forgen02.v new file mode 100644 index 000000000..14af070c3 --- /dev/null +++ b/tests/simple/forgen02.v @@ -0,0 +1,30 @@ +module uut_forgen02(a, b, cin, y, cout); + +parameter WIDTH = 8; + +input [WIDTH-1:0] a, b; +input cin; + +output [WIDTH-1:0] y; +output cout; + +genvar i; +wire [WIDTH-1:0] carry; + +generate + for (i = 0; i < WIDTH; i=i+1) begin:adder + wire [2:0] D; + assign D[1:0] = { a[i], b[i] }; + if (i == 0) begin:chain + assign D[2] = cin; + end else begin:chain + assign D[2] = carry[i-1]; + end + assign y[i] = ^D; + assign carry[i] = &D[1:0] | (^D[1:0] & D[2]); + end +endgenerate + +assign cout = carry[WIDTH-1]; + +endmodule diff --git a/tests/simple/process.v b/tests/simple/process.v index 532586649..8cb4c870e 100644 --- a/tests/simple/process.v +++ b/tests/simple/process.v @@ -1,4 +1,23 @@ +module blocking_cond (in, out); + +input in; +output reg out; +reg tmp; + +always @* begin + tmp = 1; + out = 1'b0; + case (1'b1) + tmp: out = in; + endcase + tmp = 0; +end + +endmodule + +// ------------------------------------------------------------- + module uut(clk, arst, a, b, c, d, e, f, out1); input clk, arst, a, b, c, d, e, f; diff --git a/tests/tools/vcdcd.pl b/tests/tools/vcdcd.pl index 4875eeeb0..93041534b 100755 --- a/tests/tools/vcdcd.pl +++ b/tests/tools/vcdcd.pl @@ -8,14 +8,21 @@ use Verilog::VCD qw(parse_vcd list_sigs); $| = 1; +my $opt_width = 0; +if ($ARGV[0] eq '-w') { + $opt_width = +$ARGV[1]; + shift @ARGV; + shift @ARGV; +} + if ($#ARGV != 1) { print STDERR "\n"; print STDERR "VCDCD - Value Change Dump Change Dumper\n"; print STDERR "\n"; - print STDERR "Usage: $0 gold.vcd gate.vcd\n"; + print STDERR "Usage: $0 [-w N] gold.vcd gate.vcd\n"; print STDERR "\n"; print STDERR "Compare a known-good (gold) vcd file with a second (gate) vcd file.\n"; - print STDERR "This is not very efficient -- so use with care with large vcd files.\n"; + print STDERR "This is not very efficient -- so use with care on large vcd files.\n"; print STDERR "\n"; exit 1; } @@ -112,6 +119,8 @@ for my $key (keys %$vcd_gate) { } } +$signal_maxlen = $opt_width if $opt_width > 0; + my $diffcount = 0; my %state_gold; my %state_gate; @@ -161,8 +170,11 @@ sub cmp_signal($$) my @a = split //, $a; my @b = split //, $b; - unshift @a, "-" while $#a < $#b; - unshift @b, "-" while $#b < $#a; + my $trail_a = $#a < 0 ? '-' : $a[0] eq '1' ? '0' : $a[0]; + my $trail_b = $#b < 0 ? '-' : $b[0] eq '1' ? '0' : $b[0]; + + unshift @a, $trail_a while $#a < $#b; + unshift @b, $trail_b while $#b < $#a; for (my $i = 0; $i <= $#a; $i++) { return 0 if $a[$i] ne "x" && $a[$i] ne $b[$i]; |