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-rw-r--r--tests/xilinx/mul_unsigned.ys1
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 30c034afe..77990bd68 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -4,7 +4,6 @@ hierarchy -top mul_unsigned
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
-stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 30 t:FDRE