6 files changed, 154 insertions, 0 deletions
diff --git a/tests/various/countbits.sv b/tests/various/countbits.sv
new file mode 100644
index 000000000..5762217bb
--- /dev/null
+++ b/tests/various/countbits.sv
@@ -0,0 +1,69 @@
+module top;
+
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '0            ) ==  1);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '1            ) ==  2);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, 'x            ) ==  4);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, 'z            ) ==  8);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '0, '1        ) ==  3);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '1, '1, '0    ) ==  3);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'x        ) ==  5);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'z        ) ==  9);
+	assert property ($countbits(15'bz1x10xzxzzxzzzz, '0, 'z        ) ==  9);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, 'x, 'z        ) == 12);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'z        ) == 10);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z    ) == 14);
+	assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z, '0) == 15);
+
+	assert property ($countbits(0,      '0) == 32); // test integers
+	assert property ($countbits(0,      '1) ==  0);
+	assert property ($countbits(80'b0,  '0) == 80); // test something bigger than integer
+	assert property ($countbits(80'bx0, 'x) == 79);
+
+	always_comb begin
+		logic       one;
+		logic [1:0] two;
+		logic [3:0] four;
+
+		// Make sure that the width of the whole expression doesn't affect the width of the shift
+		// operations inside the function.
+		one  = $countbits(3'b100, '1) & 1'b1;
+		two  = $countbits(3'b111, '1) & 2'b11;
+		four = $countbits(3'b111, '1) & 4'b1111;
+
+		assert (one  == 1);
+		assert (two  == 3);
+		assert (four == 3);
+	end
+
+	assert property ($countones(8'h00) == 0);
+	assert property ($countones(8'hff) == 8);
+	assert property ($countones(8'ha5) == 4);
+	assert property ($countones(8'h13) == 3);
+
+	logic       test1 = 1'b1;
+	logic [4:0] test5 = 5'b10101;
+
+	assert property ($countones(test1) == 1);
+	assert property ($countones(test5) == 3);
+
+	assert property ($isunknown(8'h00) == 0);
+	assert property ($isunknown(8'hff) == 0);
+	assert property ($isunknown(8'hx0) == 1);
+	assert property ($isunknown(8'h1z) == 1);
+	assert property ($isunknown(8'hxz) == 1);
+
+	assert property ($onehot(8'h00) == 0);
+	assert property ($onehot(8'hff) == 0);
+	assert property ($onehot(8'h01) == 1);
+	assert property ($onehot(8'h80) == 1);
+	assert property ($onehot(8'h81) == 0);
+	assert property ($onehot(8'h20) == 1);
+
+	assert property ($onehot0(8'h00) == 1);
+	assert property ($onehot0(8'hff) == 0);
+	assert property ($onehot0(8'h01) == 1);
+	assert property ($onehot0(8'h80) == 1);
+	assert property ($onehot0(8'h81) == 0);
+	assert property ($onehot0(8'h20) == 1);
+
+endmodule
diff --git a/tests/various/countbits.ys b/tests/various/countbits.ys
new file mode 100644
index 000000000..a556f7c5d
--- /dev/null
+++ b/tests/various/countbits.ys
@@ -0,0 +1,7 @@
+read_verilog -sv countbits.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/int_types.sv b/tests/verilog/int_types.sv
new file mode 100644
index 000000000..8133f8218
--- /dev/null
+++ b/tests/verilog/int_types.sv
@@ -0,0 +1,47 @@
+`define TEST(typ, width, is_signed) \
+    if (1) begin \
+        typ x = -1; \
+        localparam typ y = -1; \
+        logic [127:0] a = x; \
+        logic [127:0] b = y; \
+        if ($bits(x) != width) \
+            $error(`"typ doesn't have expected size width`"); \
+        if ($bits(x) != $bits(y)) \
+            $error(`"localparam typ doesn't match size of typ`"); \
+        function automatic typ f; \
+            input integer x; \
+            f = x; \
+        endfunction \
+        logic [127:0] c = f(-1); \
+        always @* begin \
+            assert (x == y); \
+            assert (a == b); \
+            assert (a == c); \
+            assert ((a == -1) == is_signed); \
+        end \
+    end
+
+`define TEST_INTEGER_ATOM(typ, width) \
+    `TEST(typ, width, 1) \
+    `TEST(typ signed, width, 1) \
+    `TEST(typ unsigned, width, 0)
+
+`define TEST_INTEGER_VECTOR(typ) \
+    `TEST(typ, 1, 0) \
+    `TEST(typ signed, 1, 1) \
+    `TEST(typ unsigned, 1, 0) \
+    `TEST(typ [1:0], 2, 0) \
+    `TEST(typ signed [1:0], 2, 1) \
+    `TEST(typ unsigned [1:0], 2, 0)
+
+module top;
+    `TEST_INTEGER_ATOM(integer, 32)
+    `TEST_INTEGER_ATOM(int, 32)
+    `TEST_INTEGER_ATOM(shortint, 16)
+    `TEST_INTEGER_ATOM(longint, 64)
+    `TEST_INTEGER_ATOM(byte, 8)
+
+    `TEST_INTEGER_VECTOR(reg)
+    `TEST_INTEGER_VECTOR(logic)
+    `TEST_INTEGER_VECTOR(bit)
+endmodule
diff --git a/tests/verilog/int_types.ys b/tests/verilog/int_types.ys
new file mode 100644
index 000000000..c17c44b4c
--- /dev/null
+++ b/tests/verilog/int_types.ys
@@ -0,0 +1,7 @@
+read_verilog -sv int_types.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/param_int_types.sv b/tests/verilog/param_int_types.sv
new file mode 100644
index 000000000..3228369b8
--- /dev/null
+++ b/tests/verilog/param_int_types.sv
@@ -0,0 +1,19 @@
+module gate(out);
+    parameter integer a = -1;
+    parameter int b = -2;
+    parameter shortint c = -3;
+    parameter longint d = -4;
+    parameter byte e = -5;
+    output wire [1023:0] out;
+    assign out = {a, b, c, d, e};
+endmodule
+
+module gold(out);
+    integer a = -1;
+    int b = -2;
+    shortint c = -3;
+    longint d = -4;
+    byte e = -5;
+    output wire [1023:0] out;
+    assign out = {a, b, c, d, e};
+endmodule
diff --git a/tests/verilog/param_int_types.ys b/tests/verilog/param_int_types.ys
new file mode 100644
index 000000000..7727801cf
--- /dev/null
+++ b/tests/verilog/param_int_types.ys
@@ -0,0 +1,5 @@
+read_verilog -sv param_int_types.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert