9 files changed, 127 insertions, 13 deletions
diff --git a/tests/aiger/neg.ys b/tests/aiger/neg.ys
new file mode 100644
index 000000000..4c1edd8a4
--- /dev/null
+++ b/tests/aiger/neg.ys
@@ -0,0 +1,36 @@
+read_verilog <<EOT
+module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
+assign c = a & b;
+endmodule
+EOT
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+design -save read
+
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_aiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+
+
+design -load read
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_xaiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 8e932b091..de7bc68cf 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -52,3 +52,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 16 miter
 " -l ${aig}.log
 done
+
+for y in *.ys; do
+    echo "Running $y."
+    ../../yosys $y -ql ${y%.*}.log
+done
diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
index 250273859..b13e525fd 100644
--- a/tests/arch/ice40/ice40_dsp.ys
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -8,4 +8,5 @@ assign o4 = a * b;
 SB_MAC16 m3 (.A(a), .B(b), .O(o5));
 endmodule
 EOT
+read_verilog -lib +/ice40/cells_sim.v
 ice40_dsp
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
new file mode 100644
index 000000000..4b9b54d10
--- /dev/null
+++ b/tests/arch/intel_alm/quartus_ice.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
+// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
+module top();
+  (* keep *) wire [31:0] \a[10] ;
+  (* keep *) wire b;
+  assign b = \a[10] [31];
+endmodule
+EOT
+
+synth_intel_alm -family cyclonev -quartus
+select -assert-none w:*[* w:*]*
diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys
index dc036acfd..2c729832e 100644
--- a/tests/arch/xilinx/xilinx_dffopt.ys
+++ b/tests/arch/xilinx/xilinx_dffopt.ys
@@ -18,17 +18,17 @@ FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0]));
 endmodule
 
 EOT
-
+read_verilog -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:LUT6
-select -assert-count 3 t:LUT2
-select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D
+select -assert-none t:FDRE t:LUT6 %% t:* %D
 
 design -load t0
 
@@ -36,9 +36,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:LUT4
-select -assert-count 3 t:LUT2
+select -assert-count 1 t:LUT2
 select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D
 
 design -reset
@@ -65,16 +66,17 @@ endmodule
 
 EOT
 
+read_verilog -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDSE
 select -assert-count 1 t:LUT6
-select -assert-count 3 t:LUT2
-select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D
+select -assert-none t:FDSE t:LUT6 %% t:* %D
 
 design -load t0
 
@@ -82,9 +84,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDSE
 select -assert-count 1 t:LUT4
-select -assert-count 3 t:LUT2
+select -assert-count 1 t:LUT2
 select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D
 
 design -reset
@@ -111,15 +114,17 @@ endmodule
 
 EOT
 
+read_verilog -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDCE
 select -assert-count 1 t:LUT4
-select -assert-count 3 t:LUT2
+select -assert-count 1 t:LUT2
 select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D
 
 design -reset
@@ -145,16 +150,17 @@ endmodule
 
 EOT
 
+read_verilog -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDSE
 select -assert-count 1 t:LUT5
-select -assert-count 2 t:LUT2
-select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D
+select -assert-none t:FDSE t:LUT5 %% t:* %D
 
 design -load t0
 
@@ -162,6 +168,7 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDSE
 select -assert-count 2 t:LUT2
 select -assert-none t:FDSE t:LUT2 %% t:* %D
@@ -191,16 +198,17 @@ endmodule
 
 EOT
 
+read_verilog -lib +/xilinx/cells_sim.v
 design -save t0
 
 equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDRSE
 select -assert-count 1 t:LUT6
-select -assert-count 4 t:LUT2
-select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D
+select -assert-none t:FDRSE t:LUT6 %% t:* %D
 
 design -load t0
 
@@ -208,9 +216,10 @@ equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim
 design -load postopt
 clean
 
+cd t0
 select -assert-count 1 t:FDRSE
 select -assert-count 1 t:LUT4
-select -assert-count 4 t:LUT2
+select -assert-count 1 t:LUT2
 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
 
 design -reset
diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys
index 3b9f52930..59d8296ab 100644
--- a/tests/arch/xilinx/xilinx_dsp.ys
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@@ -8,4 +8,5 @@ assign o4 = a * b;
 DSP48E1 m3 (.A(a), .B(b), .P(o5));
 endmodule
 EOT
+read_verilog -lib +/xilinx/cells_sim.v
 xilinx_dsp
diff --git a/tests/opt/bug2010.ys b/tests/opt/bug2010.ys
new file mode 100644
index 000000000..cef820867
--- /dev/null
+++ b/tests/opt/bug2010.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module test (
+        input signed [1:0] n,
+        output [3:0] dout
+);
+        assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+equiv_opt -assert opt -fine
diff --git a/tests/select/blackboxes.ys b/tests/select/blackboxes.ys
new file mode 100644
index 000000000..9bfe92c6b
--- /dev/null
+++ b/tests/select/blackboxes.ys
@@ -0,0 +1,28 @@
+read_verilog -specify <<EOT
+module top(input a, b, output o);
+assign o = a & b;
+endmodule
+
+(* blackbox *)
+module bb(input a, b, output o);
+assign o = a | b;
+specify
+	(a => o) = 1;
+endspecify
+endmodule
+
+(* whitebox *)
+module wb(input a, b, output o);
+assign o = a ^ b;
+endmodule
+EOT
+clean
+
+select -assert-count 1 c:*
+select -assert-none t:* t:$and %d
+select -assert-count 3 w:*
+select -assert-count 4 *
+
+select -assert-count 3 =c:*
+select -assert-count 10 =w:*
+select -assert-count 13 =*
diff --git a/tests/various/bug2014.ys b/tests/various/bug2014.ys
new file mode 100644
index 000000000..10131fc43
--- /dev/null
+++ b/tests/various/bug2014.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module test (
+        input signed [1:0] n,
+        output [3:0] dout
+);
+        assign dout = n + 4'sd 4;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+equiv_opt -assert opt -fine