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-rw-r--r--tests/sat/sizebits.sv (renamed from tests/simple/functions01.sv)0
-rw-r--r--tests/sat/sizebits.ys2
2 files changed, 2 insertions, 0 deletions
diff --git a/tests/simple/functions01.sv b/tests/sat/sizebits.sv
index d7ce2326e..d7ce2326e 100644
--- a/tests/simple/functions01.sv
+++ b/tests/sat/sizebits.sv
diff --git a/tests/sat/sizebits.ys b/tests/sat/sizebits.ys
new file mode 100644
index 000000000..689227a41
--- /dev/null
+++ b/tests/sat/sizebits.ys
@@ -0,0 +1,2 @@
+read_verilog -sv sizebits.sv
+prep; sat -verify -prove-asserts