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-rw-r--r--tests/rpc/frontend.py3
-rw-r--r--tests/simple/partsel.v4
-rw-r--r--tests/various/deminout_unused.ys14
3 files changed, 20 insertions, 1 deletions
diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py
index eace07bf9..8cbec5682 100644
--- a/tests/rpc/frontend.py
+++ b/tests/rpc/frontend.py
@@ -83,10 +83,11 @@ def main():
if args.mode == "unix-socket":
sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
+ sock.settimeout(30)
sock.bind(args.path)
try:
- ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
sock.listen(1)
+ ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
conn, addr = sock.accept()
file = conn.makefile("rw")
while True:
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 7461358ad..83493fcb0 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -60,3 +60,7 @@ always @(posedge clk) begin
end
endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule
diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys
new file mode 100644
index 000000000..5ed00509d
--- /dev/null
+++ b/tests/various/deminout_unused.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+module top(input clk, inout [7:0] x);
+
+reg [3:0] ctr;
+always @(posedge clk) ctr <= ctr + 1'b1;
+
+assign x[7:4] = ctr;
+endmodule
+EOT
+proc
+tribuf
+deminout
+select -assert-count 1 i:x o:x %i
+