diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/latches.ys | 9 | ||||
| -rw-r--r-- | tests/ice40/wrapcarry.ys | 22 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory.sv | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory.ys | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory_2.sv | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory_2.ys | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_package.sv | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_param.sv | 10 | ||||
| -rw-r--r-- | tests/svtypes/typedef_scopes.sv | 8 | ||||
| -rw-r--r-- | tests/svtypes/typedef_simple.sv | 10 | ||||
| -rw-r--r-- | tests/techmap/aigmap.ys | 10 | ||||
| -rw-r--r-- | tests/various/peepopt.ys | 42 | ||||
| -rw-r--r-- | tests/xilinx/latches.ys | 4 |
13 files changed, 95 insertions, 30 deletions
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index f3562559e..708734e44 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,14 +1,11 @@ read_verilog latches.v -design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load read +#design -load preopt synth_ice40 cd top select -assert-count 4 t:SB_LUT4 diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog <<EOT +module top(input A, B, CI, output O, CO); + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + SB_LUT4 #( + .LUT_INIT(16'b 0110_1001_1001_0110) + ) adder ( + .I0(1'b0), + .I1(A), + .I2(B), + .I3(1'b0), + .O(O) + ); +endmodule +EOT + +ice40_wrapcarry +select -assert-count 1 t:$__ICE40_CARRY_WRAPPER diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index 37e63c1d0..577e484ad 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] ram16x4_t[0:15]; - ram16x4_t mem; + (ram16x4_t) mem; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index d0b8cf5bf..93cf47bbe 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ -read -sv typedef_memory.sv +read_verilog -sv typedef_memory.sv prep -top top select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index 6d65131db..f3089bf55 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] nibble; - nibble mem[0:15]; + (nibble) mem[0:15]; always @(posedge clk) begin if (wen) mem[addr] <= wdata; diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 0997beeea..854e554f3 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ -read -sv typedef_memory_2.sv +read_verilog -sv typedef_memory_2.sv prep -top top dump select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index bee88b7ae..a1e16d4b1 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -4,7 +4,7 @@ endpackage module top; - (* keep *) pkg::uint8_t a = 8'hAA; + (* keep *) (pkg::uint8_t) a = 8'hAA; always @* assert(a == 8'hAA); diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index d838dd828..ddbd471e0 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -6,12 +6,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef int8_t char_t; + typedef (int8_t) char_t; - parameter uint2_t int2 = 2'b10; - localparam int4_t int4 = -1; - localparam int8_t int8 = int4; - localparam char_t ch = int8; + parameter (uint2_t) int2 = 2'b10; + localparam (int4_t) int4 = -1; + localparam (int8_t) int8 = int4; + localparam (char_t) ch = int8; `STATIC_ASSERT(int2 == 2'b10); diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index 340defbbb..faa385bd6 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -3,20 +3,20 @@ typedef logic [3:0] outer_uint4_t; module top; - outer_uint4_t u4_i = 8'hA5; + (outer_uint4_t) u4_i = 8'hA5; always @(*) assert(u4_i == 4'h5); typedef logic [3:0] inner_type; - inner_type inner_i1 = 8'h5A; + (inner_type) inner_i1 = 8'h5A; always @(*) assert(inner_i1 == 4'hA); if (1) begin: genblock typedef logic [7:0] inner_type; - inner_type inner_gb_i = 8'hA5; + (inner_type) inner_gb_i = 8'hA5; always @(*) assert(inner_gb_i == 8'hA5); end - inner_type inner_i2 = 8'h42; + (inner_type) inner_i2 = 8'h42; always @(*) assert(inner_i2 == 4'h2); diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 8f89910e5..7e760dee4 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -3,12 +3,12 @@ module top; typedef logic [1:0] uint2_t; typedef logic signed [3:0] int4_t; typedef logic signed [7:0] int8_t; - typedef int8_t char_t; + typedef (int8_t) char_t; - (* keep *) uint2_t int2 = 2'b10; - (* keep *) int4_t int4 = -1; - (* keep *) int8_t int8 = int4; - (* keep *) char_t ch = int8; + (* keep *) (uint2_t) int2 = 2'b10; + (* keep *) (int4_t) int4 = -1; + (* keep *) (int8_t) int8 = int4; + (* keep *) (char_t) ch = int8; always @* assert(int2 == 2'b10); diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys new file mode 100644 index 000000000..a40aa39f1 --- /dev/null +++ b/tests/techmap/aigmap.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module top(input i, j, s, output o, p); +assign o = s ? j : i; +assign p = ~i; +endmodule +EOT + +select t:$mux +aigmap -select +select -assert-any % diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 6bca62e2b..ee5ad8a1a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -131,8 +131,8 @@ EOT proc equiv_opt -assert peepopt design -load postopt -select -assert-count 1 t:$dff r:WIDTH=5 %i -select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 1 t:$dff r:WIDTH=4 %i +select -assert-count 1 t:$mux r:WIDTH=4 %i select -assert-count 0 t:$dff t:$mux %% t:* %D #################### @@ -173,3 +173,41 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + initial o <= 4'b0010; + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +# NB: equiv_opt uses equiv_induct which covers +# only the induction half of temporal induction +# --- missing the base-case half +# This makes it akin to `sat -tempinduct-inductonly` +# instead of `sat -tempinduct-baseonly` or +# `sat -tempinduct` which is necessary for this +# testcase +#equiv_opt -assert peepopt + +design -save gold +peepopt +wreduce +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -tempinduct -verify -prove-asserts -show-ports miter + +design -load gate +select -assert-count 1 t:$dff r:WIDTH=4 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=4 %i +select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index ac1102896..bd1dffd21 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,9 +2,7 @@ read_verilog latches.v proc flatten -equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -async2sync -equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load preopt synth_xilinx |