5 files changed, 79 insertions, 0 deletions
diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
new file mode 100644
index 000000000..75c4cd136
--- /dev/null
+++ b/tests/simple/macro_arg_spaces.sv
@@ -0,0 +1,28 @@
+module top(
+	input wire [31:0] i,
+	output wire [31:0] x, y, z
+);
+
+`define BAR(a) a
+`define FOO(a = function automatic [31:0] f) a
+
+`BAR(function automatic [31:0] a);
+	input [31:0] i;
+	a = i * 2;
+endfunction
+
+`FOO();
+	input [31:0] i;
+	f = i * 3;
+endfunction
+
+`FOO(function automatic [31:0] b);
+	input [31:0] i;
+	b = i * 5;
+endfunction
+
+assign x = a(i);
+assign y = f(i);
+assign z = b(i);
+
+endmodule
diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv
new file mode 100644
index 000000000..be00812c0
--- /dev/null
+++ b/tests/various/rand_const.sv
@@ -0,0 +1,8 @@
+module top;
+	rand const reg rx;
+	const reg ry;
+	rand reg rz;
+	rand const integer ix;
+	const integer iy;
+	rand integer iz;
+endmodule
diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys
new file mode 100644
index 000000000..74e43c7cc
--- /dev/null
+++ b/tests/various/rand_const.ys
@@ -0,0 +1 @@
+read_verilog -sv rand_const.sv
diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv
new file mode 100644
index 000000000..79c7c04c6
--- /dev/null
+++ b/tests/verilog/wire_and_var.sv
@@ -0,0 +1,33 @@
+`define TEST(kwd) \
+	kwd kwd``_1; \
+	kwd kwd``_2; \
+	initial kwd``_1 = 1; \
+	assign kwd``_2 = 1;
+
+`define TEST_VAR(kwd) \
+	var kwd var_``kwd``_1; \
+	var kwd var_``kwd``_2; \
+	initial var_``kwd``_1 = 1; \
+	assign var_``kwd``_2 = 1;
+
+`define TEST_WIRE(kwd) \
+	wire kwd wire_``kwd``_1; \
+	wire kwd wire_``kwd``_2; \
+	initial wire_``kwd``_1 = 1; \
+	assign wire_``kwd``_2 = 1;
+
+module top;
+
+`TEST(wire) // wire assigned in a block
+`TEST(reg) // reg assigned in a continuous assignment
+`TEST(logic)
+`TEST(integer)
+
+`TEST_VAR(reg) // reg assigned in a continuous assignment
+`TEST_VAR(logic)
+`TEST_VAR(integer)
+
+`TEST_WIRE(logic) // wire assigned in a block
+`TEST_WIRE(integer) // wire assigned in a block
+
+endmodule
diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys
new file mode 100644
index 000000000..9359a9d55
--- /dev/null
+++ b/tests/verilog/wire_and_var.ys
@@ -0,0 +1,9 @@
+logger -expect warning "wire '\\wire_1' is assigned in a block" 1
+logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
+logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+
+read_verilog -sv wire_and_var.sv