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-rw-r--r--tests/bram/generate.py28
-rw-r--r--tests/opt/opt_clean_mem.ys1
-rw-r--r--tests/proc/bug2619.ys23
-rwxr-xr-xtests/tools/autotest.sh2
-rw-r--r--tests/verilog/absurd_width.ys17
-rw-r--r--tests/verilog/absurd_width_const.ys16
-rw-r--r--tests/verilog/localparam_no_default_1.ys17
-rw-r--r--tests/verilog/localparam_no_default_2.ys15
-rw-r--r--tests/verilog/param_no_default.sv52
-rw-r--r--tests/verilog/param_no_default.ys7
-rw-r--r--tests/verilog/param_no_default_not_svmode.ys26
-rw-r--r--tests/verilog/param_no_default_unbound_1.ys12
-rw-r--r--tests/verilog/param_no_default_unbound_2.ys12
-rw-r--r--tests/verilog/param_no_default_unbound_3.ys12
-rw-r--r--tests/verilog/param_no_default_unbound_4.ys12
-rw-r--r--tests/verilog/param_no_default_unbound_5.ys12
-rw-r--r--tests/verilog/unbased_unsized.sv40
-rw-r--r--tests/verilog/unbased_unsized.ys7
18 files changed, 304 insertions, 7 deletions
diff --git a/tests/bram/generate.py b/tests/bram/generate.py
index def0b23c1..79dd500a3 100644
--- a/tests/bram/generate.py
+++ b/tests/bram/generate.py
@@ -93,18 +93,22 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
tb_dout = list()
tb_addrlist = list()
+ addrmask = (1 << abits) - 1
+
for i in range(10):
- tb_addrlist.append(random.randrange(1048576))
+ tb_addrlist.append(random.randrange(1048576) & addrmask)
t = random.randrange(1048576)
for i in range(10):
- tb_addrlist.append(t ^ (1 << i))
+ tb_addrlist.append((t ^ (1 << i)) & addrmask)
v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
portindex = 0
last_always_hdr = (-1, "")
+ addr2en = {}
+
for p1 in range(groups):
for p2 in range(ports[p1]):
pf = "%c%d" % (chr(ord("A") + p1), p2 + 1)
@@ -143,6 +147,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf))
tb_decls.append("reg [%d:0] %sEN;" % (enable[p1]-1, pf))
tb_din.append("%sEN" % pf)
+ addr2en["%sADDR" % pf] = "%sEN" % pf
assign_op = "<="
if clocks[p1] == 0:
@@ -247,10 +252,23 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
print(" #100;", file=tb_f)
print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
(k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
- for p in tb_din:
- print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f)
+ a2e = {}
for p in tb_addr:
- print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
+ addr = random.choice(tb_addrlist)
+ if p in addr2en:
+ if addr not in a2e:
+ a2e[addr] = []
+ a2e[addr].append(addr2en[p])
+ print(" %s <= %d;" % (p, addr), file=tb_f)
+ enzero = set()
+ for v in a2e.values():
+ x = random.choice(v)
+ for s in v:
+ if s != x:
+ enzero.add(s)
+ for p in tb_din:
+ val = 0 if p in enzero else random.randrange(1048576)
+ print(" %s <= %d;" % (p, val), file=tb_f)
print(" #900;", file=tb_f)
print(" end", file=tb_f)
diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys
index b35b15871..d08943da4 100644
--- a/tests/opt/opt_clean_mem.ys
+++ b/tests/opt/opt_clean_mem.ys
@@ -22,7 +22,6 @@ endmodule
EOT
proc
-memory_dff
select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr
diff --git a/tests/proc/bug2619.ys b/tests/proc/bug2619.ys
new file mode 100644
index 000000000..a080b94f5
--- /dev/null
+++ b/tests/proc/bug2619.ys
@@ -0,0 +1,23 @@
+read_verilog << EOT
+
+module top(...);
+
+input D1, D2, R, CLK;
+output reg Q1, Q2;
+
+always @(posedge CLK, posedge R) begin
+ Q1 <= 0;
+ if (!R) begin
+ Q1 <= D1;
+ Q2 <= D2;
+ end
+end
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 1 t:$adff
+select -assert-count 1 t:$dffe
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 72a3d51eb..e4aef9917 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -197,7 +197,7 @@ do
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
- "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
+ "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
fi
diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys
new file mode 100644
index 000000000..c0d2af4c2
--- /dev/null
+++ b/tests/verilog/absurd_width.ys
@@ -0,0 +1,17 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+ input inp,
+ output out
+);
+ assign out =
+ {1024 {
+ {1024 {
+ {1024 {
+ inp
+ }}
+ }}
+ }}
+ ;
+endmodule
+EOF
diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys
new file mode 100644
index 000000000..b7191fd0d
--- /dev/null
+++ b/tests/verilog/absurd_width_const.ys
@@ -0,0 +1,16 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+ output out
+);
+ assign out =
+ {1024 {
+ {1024 {
+ {1024 {
+ 1'b1
+ }}
+ }}
+ }}
+ ;
+endmodule
+EOF
diff --git a/tests/verilog/localparam_no_default_1.ys b/tests/verilog/localparam_no_default_1.ys
new file mode 100644
index 000000000..426a48a1c
--- /dev/null
+++ b/tests/verilog/localparam_no_default_1.ys
@@ -0,0 +1,17 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module #(
+ localparam X = 1
+);
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "localparam initialization is missing!" 1
+read_verilog <<EOF
+module Module #(
+ localparam X
+);
+endmodule
+EOF
diff --git a/tests/verilog/localparam_no_default_2.ys b/tests/verilog/localparam_no_default_2.ys
new file mode 100644
index 000000000..b7b2622ad
--- /dev/null
+++ b/tests/verilog/localparam_no_default_2.ys
@@ -0,0 +1,15 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module;
+ localparam X = 1;
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "localparam initialization is missing!" 1
+read_verilog <<EOF
+module Module;
+ localparam X;
+endmodule
+EOF
diff --git a/tests/verilog/param_no_default.sv b/tests/verilog/param_no_default.sv
new file mode 100644
index 000000000..cc35bd2ea
--- /dev/null
+++ b/tests/verilog/param_no_default.sv
@@ -0,0 +1,52 @@
+module example #(
+ parameter w,
+ parameter x = 1,
+ parameter byte y,
+ parameter byte z = 3
+) (
+ output a, b,
+ output byte c, d
+);
+ assign a = w;
+ assign b = x;
+ assign c = y;
+ assign d = z;
+endmodule
+
+module top;
+ wire a1, b1;
+ wire a2, b2;
+ wire a3, b3;
+ wire a4, b4;
+ byte c1, d1;
+ byte c2, d2;
+ byte c3, d3;
+ byte c4, d4;
+
+ example #(0, 1, 2) e1(a1, b1, c1, d1);
+ example #(.w(1), .y(4)) e2(a2, b2, c2, d2);
+ example #(.x(0), .w(1), .y(5)) e3(a3, b3, c3, d3);
+ example #(1, 0, 9, 10) e4(a4, b4, c4, d4);
+
+ always @* begin
+ assert (a1 == 0);
+ assert (b1 == 1);
+ assert (c1 == 2);
+ assert (d1 == 3);
+
+ assert (a2 == 1);
+ assert (b2 == 1);
+ assert (c2 == 4);
+ assert (d3 == 3);
+
+ assert (a3 == 1);
+ assert (b3 == 0);
+ assert (c3 == 5);
+ assert (d3 == 3);
+
+ assert (a4 == 1);
+ assert (b4 == 0);
+ assert (c4 == 9);
+ assert (d4 == 10);
+ end
+endmodule
diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys
new file mode 100644
index 000000000..7f161a909
--- /dev/null
+++ b/tests/verilog/param_no_default.ys
@@ -0,0 +1,7 @@
+read_verilog -sv param_no_default.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/param_no_default_not_svmode.ys b/tests/verilog/param_no_default_not_svmode.ys
new file mode 100644
index 000000000..1ded84e9c
--- /dev/null
+++ b/tests/verilog/param_no_default_not_svmode.ys
@@ -0,0 +1,26 @@
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module;
+ parameter X;
+endmodule
+EOF
+
+design -reset
+
+logger -expect-no-warnings
+read_verilog -sv <<EOF
+module Module #(
+ parameter X
+);
+endmodule
+EOF
+
+design -reset
+
+logger -expect error "Parameter defaults can only be omitted in SystemVerilog mode!" 1
+read_verilog <<EOF
+module Module #(
+ parameter X
+);
+endmodule
+EOF
diff --git a/tests/verilog/param_no_default_unbound_1.ys b/tests/verilog/param_no_default_unbound_1.ys
new file mode 100644
index 000000000..4aab85ab5
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_1.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+ parameter X
+);
+endmodule
+module top;
+ Example e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_2.ys b/tests/verilog/param_no_default_unbound_2.ys
new file mode 100644
index 000000000..4b7f3b028
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_2.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+ parameter X, Y
+);
+endmodule
+module top;
+ Example e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_3.ys b/tests/verilog/param_no_default_unbound_3.ys
new file mode 100644
index 000000000..f32b879a5
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_3.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+ parameter X, Y
+);
+endmodule
+module top;
+ Example #(1) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_4.ys b/tests/verilog/param_no_default_unbound_4.ys
new file mode 100644
index 000000000..3a8d69d78
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_4.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+ parameter X, Y
+);
+endmodule
+module top;
+ Example #(.Y(1)) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/param_no_default_unbound_5.ys b/tests/verilog/param_no_default_unbound_5.ys
new file mode 100644
index 000000000..30282eba7
--- /dev/null
+++ b/tests/verilog/param_no_default_unbound_5.ys
@@ -0,0 +1,12 @@
+read_verilog -sv <<EOF
+module Example #(
+ parameter X, Y = 2
+);
+endmodule
+module top;
+ Example #(.Y(1)) e();
+endmodule
+EOF
+
+logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1
+hierarchy -top top
diff --git a/tests/verilog/unbased_unsized.sv b/tests/verilog/unbased_unsized.sv
new file mode 100644
index 000000000..1d0c5a72c
--- /dev/null
+++ b/tests/verilog/unbased_unsized.sv
@@ -0,0 +1,40 @@
+module pass_through(
+ input [63:0] inp,
+ output [63:0] out
+);
+ assign out = inp;
+endmodule
+
+module top;
+ logic [63:0]
+ o01, o02, o03, o04,
+ o05, o06, o07, o08,
+ o09, o10, o11, o12,
+ o13, o14, o15, o16;
+ assign o01 = '0;
+ assign o02 = '1;
+ assign o03 = 'x;
+ assign o04 = 'z;
+ assign o05 = 3'('0);
+ assign o06 = 3'('1);
+ assign o07 = 3'('x);
+ assign o08 = 3'('z);
+ pass_through pt09('0, o09);
+ pass_through pt10('1, o10);
+ pass_through pt11('x, o11);
+ pass_through pt12('z, o12);
+ always @* begin
+ assert (o01 === {64 {1'b0}});
+ assert (o02 === {64 {1'b1}});
+ assert (o03 === {64 {1'bx}});
+ assert (o04 === {64 {1'bz}});
+ assert (o05 === {61'b0, 3'b000});
+ assert (o06 === {61'b0, 3'b111});
+ assert (o07 === {61'b0, 3'bxxx});
+ assert (o08 === {61'b0, 3'bzzz});
+ assert (o09 === {64 {1'b0}});
+ assert (o10 === {64 {1'b1}});
+ assert (o11 === {64 {1'bx}});
+ assert (o12 === {64 {1'bz}});
+ end
+endmodule
diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys
new file mode 100644
index 000000000..e1bc99c64
--- /dev/null
+++ b/tests/verilog/unbased_unsized.ys
@@ -0,0 +1,7 @@
+read_verilog -sv unbased_unsized.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-03 19:13:10 +0000