| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Re-enable partsel.v test | Eddie Hung | 2019-04-16 | 1 | -1/+0 |
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| * | abc9 to call "setundef -zero" behaving as for abc | Eddie Hung | 2019-04-16 | 1 | -0/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-15 | 3 | -6/+5 |
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| | * | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| | |\ | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | ||||
| | | * | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 |
| | |/ | | | | | | | #931)" | ||||
| | * | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 |
| | |\ | | | | | | | README: fix some incorrect quoting | ||||
| | | * | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
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| * | | Forgot backslashes | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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| * | | Handle __dummy_o__ and __const[01]__ in read_aiger not abc | Eddie Hung | 2019-04-12 | 2 | -18/+8 |
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| * | | abc to ignore __dummy_o__ and __const[01]__ when re-integrating | Eddie Hung | 2019-04-12 | 1 | -6/+20 |
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| * | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 |
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| * | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 1 | -12/+32 |
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| | * | | Fix inout handling for -map option | Eddie Hung | 2019-04-12 | 1 | -10/+30 |
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| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-04-12 | 0 | -0/+0 |
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| | * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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| * | | | Use -map instead of -symbols for aiger | Eddie Hung | 2019-04-12 | 1 | -2/+3 |
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| * | | | ci_bits and co_bits now a list, order is important for ABC | Eddie Hung | 2019-04-12 | 1 | -24/+34 |
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| * | | | Also cope with duplicated CIs | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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| * | | | WIP | Eddie Hung | 2019-04-12 | 1 | -14/+68 |
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| * | | | Comment out | Eddie Hung | 2019-04-12 | 1 | -1/+1 |
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| * | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 2 | -1/+14 |
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| * | | | Cope with an output having same name as an input (i.e. CO) | Eddie Hung | 2019-04-12 | 1 | -5/+23 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 7 | -50/+76 |
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| | * | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
| | |\ | | | | | | | Add additional cells sim models for core 7-series primitives. | ||||
| | | * | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
| | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | * | | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 |
| | |\ \ | | | | | | | | | Fixing issues in CycloneV cell sim | ||||
| | | * | | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| | * | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 |
| | |\ \ | | |/ | |/| | Recognise default entry in case even if all cases covered (fix for #931) | ||||
| | | * | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 |
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| | | * | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 |
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| | * | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 |
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| * | | Add non-input bits driven by unrecognised cells as ci_bits | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
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| * | | parse_aiger() to rename all $lut cells after "clean" | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
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| * | | More space fixing | Eddie Hung | 2019-04-08 | 1 | -2/+2 |
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| * | | Fix spacing | Eddie Hung | 2019-04-08 | 1 | -29/+29 |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 115 | -710/+5842 |
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| | * | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 |
| | |\ | | | | | | | memory_bram: Fix multiport make_transp | ||||
| | | * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #913 from smunaut/fix_proc_mux | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
| | |\ | | | | | | | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | ||||
| | | * | proc_mux: Fix crash when trying to optimize non-existant mux to shiftx | Sylvain Munaut | 2019-04-03 | 1 | -1/+1 |
| | |/ | | | | | | | | | | | last_mux_cell can be NULL ... Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | Merge pull request #912 from YosysHQ/bram_addr_en | Clifford Wolf | 2019-04-03 | 1 | -0/+2 |
| | |\ | | | | | | | memory_bram: Consider read enable for address expansion register | ||||
| | | * | memory_bram: Consider read enable for address expansion register | David Shah | 2019-04-02 | 1 | -0/+2 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | Merge pull request #910 from ucb-bar/memupdates | Clifford Wolf | 2019-04-03 | 1 | -30/+173 |
| | |\ \ | | |/ | |/| | Refine memory support to deal with general Verilog memory definitions. | ||||
| | | * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 |
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| | * | | Merge pull request #895 from YosysHQ/pmux2shiftx | Eddie Hung | 2019-04-02 | 1 | -0/+28 |
| | |\ \ | | |/ | |/| | RFC: Add a pmux-to-shiftx optimisation to proc_mux | ||||
| | | * | Create one $shiftx per bit in width | Eddie Hung | 2019-03-25 | 1 | -10/+17 |
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