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Add TODO to parse_xaiger
Eddie Hung
2019-06-14
1
-0
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+1
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Optimise some more
Eddie Hung
2019-06-13
1
-58
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+53
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Move ConstEvalAig to aigerparse.cc
Eddie Hung
2019-06-13
2
-160
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+161
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Fix name clash
Eddie Hung
2019-06-13
1
-4
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+8
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More slimming
Eddie Hung
2019-06-13
1
-35
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+35
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Add ConstEvalAig specialised for AIGs
Eddie Hung
2019-06-13
2
-3
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+159
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Update CHANGELOG with "synth -abc9"
Eddie Hung
2019-06-13
1
-0
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+1
*
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Fix LP SB_LUT4 timing
Eddie Hung
2019-06-13
1
-1
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+1
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More accurate CHANGELOG
Eddie Hung
2019-06-13
1
-1
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+3
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Update CHANGELOG
Eddie Hung
2019-06-12
1
-0
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+1
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Rip out all non FPGA stuff from abc9
Eddie Hung
2019-06-12
1
-343
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+111
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Fix spelling
Eddie Hung
2019-06-12
1
-1
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+1
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Revert "For 'stat' do not count modules with abc_box_id"
Eddie Hung
2019-06-12
1
-3
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+0
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
Eddie Hung
2019-06-12
2
-247
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+0
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-06-12
1
-0
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+8
*
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Be more precise when connecting during ABC9 re-integration
Eddie Hung
2019-06-12
1
-1
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+3
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Remove unnecessary undriven_bits.insert
Eddie Hung
2019-06-12
1
-4
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+1
*
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Remove hacky wideports_split from abc9
Eddie Hung
2019-06-12
1
-52
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+4
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Fix compile errors when #if 1 for debug
Eddie Hung
2019-06-12
1
-7
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+8
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parse_xaiger to cope with inouts
Eddie Hung
2019-06-12
1
-6
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+0
*
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write_xaiger to preserve POs even if driven by constant
Eddie Hung
2019-06-12
1
-7
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+6
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Add a couple more tests
Eddie Hung
2019-06-12
2
-21
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+30
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Do not call abc9 if no outputs
Eddie Hung
2019-06-12
1
-54
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+65
*
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More write_xaiger cleanup
Eddie Hung
2019-06-12
2
-41
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+13
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Cleanup write_xaiger
Eddie Hung
2019-06-12
1
-92
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+6
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Consistency
Eddie Hung
2019-06-12
4
-4
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+4
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Reduce diff with master
Eddie Hung
2019-06-12
1
-1
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+1
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Remove abc_flop{,_d} attributes from ice40/cells_sim.v
Eddie Hung
2019-06-12
1
-40
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+20
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Fix spacing
Eddie Hung
2019-06-12
1
-6
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+6
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Remove wide mux inference
Eddie Hung
2019-06-12
5
-195
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+3
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Merge branch 'xc7mux' into xaig
Eddie Hung
2019-06-12
1
-1
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+1
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Merge branch 'xc7mux' of github.com:YosysHQ/yosys into xc7mux
Eddie Hung
2019-06-12
1
-0
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+5
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Typo: wire delay is -W argument
Eddie Hung
2019-06-12
1
-1
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+1
*
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Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...
Eddie Hung
2019-06-12
3
-59
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+3
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
Eddie Hung
2019-06-12
3
-268
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+0
*
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
Eddie Hung
2019-06-12
3
-55
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+10
*
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Merge remote-tracking branch 'origin/xc7mux' into xaig
Eddie Hung
2019-06-12
34
-518
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+1434
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Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
2
-6
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+14
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Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
3
-14
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+11
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Add "-W' wire delay arg to abc9, use from synth_xilinx
Eddie Hung
2019-06-11
3
-11
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+14
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Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...
Eddie Hung
2019-06-11
1
-15
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+10
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*
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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-11
1
-10
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+15
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Try way that doesn't involve creating a new wire
Eddie Hung
2019-06-11
1
-10
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+15
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*
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Disable dist RAM boxes due to comb loop
Eddie Hung
2019-06-11
1
-2
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+2
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Remove #ifndef ABC
Eddie Hung
2019-06-11
1
-4
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+0
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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-10
3
-3
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+59
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If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung
2019-06-10
1
-3
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+6
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Add test
Eddie Hung
2019-06-10
2
-0
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+53
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Revert "Revert "Move ff_map back after ABC for shregmap""
Eddie Hung
2019-06-10
1
-5
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+5
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*
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Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
Eddie Hung
2019-06-10
2
-6
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+6
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