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Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173, resulting in warnings in
frontends/ast/simplify.cc:
frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
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Use C++11 final/override/[[noreturn]]
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Fix GitHub misidentifying *.v files as Coq
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cxxrtl: add .get() and .set() accessors on value<> and wire<>
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For several reasons:
* They're more convenient than accessing .data.
* They accommodate variably-sized types like size_t transparently.
* They statically ensure that no out of range conversions happen.
For now these are only provided for unsigned integers, but eventually
they should be provided for signed integers too. (Annoyingly this
affects conversions to/from `char` at the moment.)
Fixes #2127.
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cutpoint: Improve efficiency by iterating over module ports instead of module wires
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module wires.
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splitnets: Cleanup and efficiency improvements
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cxxrtl: don't compute vital values in log_assert()
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This breaks NDEBUG builds.
Fixes #2166.
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splitnets: propagate (*hdlname*) and disambiguate via start_offset
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This allows reliably coalescing the split wires later.
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Get yosys building on Visual Studio
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cxxrtl: restrict the debug info of a blackbox to its ports.
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cxxrtl: avoid unused variable warning for transparent $memrd ports
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Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
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cxxrtl: Implement chunk-wise multiplication
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cxxrtl: fix sshr sign-extension.
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kernel: guard include of signal.h more precisely
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Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
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cxxrtl: fix rzext()
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This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
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cxxrtl: handle multipart signals
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This avoids losing design visibility when using the `splitnets` pass.
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cxxrtl: always inline internal cells and slice/concat operations
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This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.
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cxxrtl: elide $pmux cells
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On Minerva, this improves runtime by around 10%, mostly by ensuring
that the logic driving FFs is packed into edge conditionals.
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cxxrtl: unbuffer output wires of toplevel module
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Without unbuffering output wires of, at least, toplevel modules, it
is not possible to have most designs that rely on IO via toplevel
ports (as opposed to using exclusively blackboxes) converge within
one delta cycle. That seriously impairs the performance of CXXRTL.
This commit avoids unbuffering outputs of all modules solely so that
in future, CXXRTL could gain fully separate compilation, and not for
any present technical reason.
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This also fixes an edge case with (*keep*) input ports.
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cxxrtl: various compiler compatibility fixes
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This is necessary to be able to build CXXRTL models via yosys-config.
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