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Age
Files
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*
Added previousely missed functions
Benedikt Tutzer
2018-08-21
1
-1
/
+445
*
Deleted duplicate Destructor
Benedikt Tutzer
2018-08-21
1
-1
/
+0
*
added some checks if python is enabled to make sure everything compiles if py...
Benedikt Tutzer
2018-08-20
5
-7
/
+12
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Two passes are not allowed to have the same filename
Benedikt Tutzer
2018-08-20
1
-1
/
+1
*
The share directory cannot be searched when used as a Python library, only in...
Benedikt Tutzer
2018-08-20
2
-1
/
+8
*
Python passes are now looked for in share/plugins and can be added by specify...
Benedikt Tutzer
2018-08-20
2
-24
/
+5
*
Fixed issue when using a python plugin in the yosys shell
Benedikt Tutzer
2018-08-20
3
-4
/
+28
*
Python Passes can now be added with the -m option or with the plugin command....
Benedikt Tutzer
2018-08-16
5
-2
/
+160
*
Added Wrappers for:
Benedikt Tutzer
2018-08-13
4
-144
/
+2925
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Saving id and pointer to c++ object. Object is valid only if both id and poin...
Benedikt Tutzer
2018-08-01
1
-8
/
+29
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Setup is called automatically when the module is loaded, shutdown when python...
Benedikt Tutzer
2018-08-01
1
-16
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+19
*
Cleaned up comments
Benedikt Tutzer
2018-08-01
1
-9
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+3
*
removed unused library and already present compiler flag
Benedikt Tutzer
2018-08-01
1
-3
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+3
*
Added Monitor class that can monitor all changes in a Design or in a Module
Benedikt Tutzer
2018-07-10
1
-0
/
+119
*
added destructors for wires and cells
Benedikt Tutzer
2018-07-10
2
-1
/
+16
*
removed debug output
Benedikt Tutzer
2018-07-09
1
-1
/
+0
*
commands can now be run on arbitrary designs, not only on the active one
Benedikt Tutzer
2018-07-09
1
-0
/
+10
*
multiple designs can now exist independent from each other. Cells/Wires/Modul...
Benedikt Tutzer
2018-07-09
3
-45
/
+118
*
Introduced namespace and removed class-prefixes to increase readability
Benedikt Tutzer
2018-06-28
1
-163
/
+165
*
changed references from hash-ids to IdString names
Benedikt Tutzer
2018-06-28
1
-64
/
+32
*
added wrappers for Design, Modules, Cells and Wires
Benedikt Tutzer
2018-06-25
2
-0
/
+245
*
added ENABLE_PYTHON option in build environment
Benedikt Tutzer
2018-06-22
1
-1
/
+10
*
Add simplified "read" command, enable extnets in implicit Verific import
Clifford Wolf
2018-06-21
1
-0
/
+84
*
Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf
2018-06-20
1
-1
/
+1
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Merge pull request #572 from q3k/q3k/fix-protobuf-build
Clifford Wolf
2018-06-20
1
-1
/
+1
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Fix protobuf build
Sergiusz Bazanski
2018-06-20
1
-1
/
+1
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Add automatic verific import in hierarchy command
Clifford Wolf
2018-06-20
3
-1
/
+75
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/
*
Merge pull request #571 from q3k/q3k/protobuf-backend
Clifford Wolf
2018-06-19
5
-0
/
+560
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Add Protobuf backend
Serge Bazanski
2018-06-19
5
-0
/
+560
*
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Be slightly less aggressive in "deminout" pass
Clifford Wolf
2018-06-19
1
-4
/
+28
*
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Merge pull request #570 from edcote/patch-4
Clifford Wolf
2018-06-19
1
-4
/
+4
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Include module name for area summary stats
Edmond Cote
2018-06-18
1
-4
/
+4
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/
*
Bugfix in liberty parser (as suggested by aiju in #569)
Clifford Wolf
2018-06-15
1
-1
/
+1
*
Add "synth_ice40 -json"
Clifford Wolf
2018-06-13
1
-9
/
+22
*
Fix ice40_opt for cases where a port is connected to a signal with width != 1
Clifford Wolf
2018-06-11
1
-9
/
+25
*
Merge pull request #561 from udif/pr_skip_typo
Clifford Wolf
2018-06-06
1
-1
/
+1
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Fixed typo (sikp -> skip)
Udi Finkelstein
2018-06-05
1
-1
/
+1
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/
*
Add (* gclk *) attribute support
Clifford Wolf
2018-06-01
4
-1
/
+23
*
Add setundef -anyseq / -anyconst support to -undriven mode
Clifford Wolf
2018-06-01
1
-3
/
+11
*
Add "setundef -anyconst"
Clifford Wolf
2018-06-01
1
-20
/
+41
*
Bugfix in handling of array instances with empty ports
Clifford Wolf
2018-05-31
1
-1
/
+1
*
Update examples/cmos/counter.ys to use "synth" command
Clifford Wolf
2018-05-30
1
-5
/
+5
*
Make -nordff the default in "prep"
Clifford Wolf
2018-05-30
1
-9
/
+13
*
Update ABC to git rev 6df1396
Clifford Wolf
2018-05-30
1
-1
/
+1
*
Disable memory_dff for initialized FFs
Clifford Wolf
2018-05-28
1
-1
/
+19
*
Add some cleanup code to memory_nordff
Clifford Wolf
2018-05-28
1
-26
/
+36
*
Add comment to VIPER #13453 work-around
Clifford Wolf
2018-05-28
1
-0
/
+1
*
Fix Verific handling of single-bit anyseq/anyconst wires
Clifford Wolf
2018-05-25
1
-2
/
+4
*
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
Clifford Wolf
2018-05-24
1
-1
/
+1
*
Fix verific handling of anyconst/anyseq attributes
Clifford Wolf
2018-05-24
2
-16
/
+28
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