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Age
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*
Improve SMT2 encoding of $reduce_{and,or,bool}
Clifford Wolf
2018-03-04
1
-1
/
+9
*
Fix a hangup in yosys-smtbmc error handling
Clifford Wolf
2018-03-04
1
-3
/
+5
*
Add proper SVA seq.triggered support
Clifford Wolf
2018-03-04
3
-37
/
+102
*
Add "synth -noshare"
Clifford Wolf
2018-03-04
1
-2
/
+11
*
Add Verific SVA support for "seq and seq" expressions
Clifford Wolf
2018-03-04
1
-24
/
+94
*
Refactor Verific SVA importer property parser
Clifford Wolf
2018-03-04
1
-56
/
+82
*
Add VerificClocking class and refactor Verific DFF handling
Clifford Wolf
2018-03-04
3
-126
/
+196
*
Improved error handling in yosys-smtbmc
Clifford Wolf
2018-03-03
1
-1
/
+3
*
Add SVA support for sequence OR
Clifford Wolf
2018-03-03
1
-22
/
+33
*
Terminate running SMT solver when smtbmc is terminated
Clifford Wolf
2018-03-03
1
-1
/
+31
*
Fix smtbmc smtc/aiw parser for wire names containing []
Clifford Wolf
2018-03-03
1
-1
/
+1
*
Fix handling of SVA "until seq.triggered" properties
Clifford Wolf
2018-03-02
1
-7
/
+25
*
Update SVA cheat sheet in verificsva.cc
Clifford Wolf
2018-03-02
1
-2
/
+4
*
Fix in Verific SVA importer handling of until_with
Clifford Wolf
2018-03-01
1
-7
/
+5
*
Mangle names with square brackets in VCD files to work around issues in gtkwave
Clifford Wolf
2018-03-01
1
-2
/
+8
*
Fixes and improvements in Verific SVA importer
Clifford Wolf
2018-03-01
3
-83
/
+136
*
Add $rose/$fell support to Verific bindings
Clifford Wolf
2018-03-01
1
-3
/
+22
*
Merge branch 'verificsva-ng'
Clifford Wolf
2018-02-28
4
-403
/
+752
|
\
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*
Add support for PRIM_SVA_UNTIL to new SVA importer
Clifford Wolf
2018-02-28
1
-0
/
+27
|
*
Add DFSM generator to verific SVA importer
Clifford Wolf
2018-02-28
1
-19
/
+272
|
*
Continue refactoring of Verific SVA importer code
Clifford Wolf
2018-02-28
3
-671
/
+172
|
*
Major redesign of Verific SVA importer
Clifford Wolf
2018-02-27
2
-6
/
+574
|
/
*
Add -lz for verific builds
Clifford Wolf
2018-02-27
1
-1
/
+1
*
Add handling of verific OPER_REDUCE_NOR
Clifford Wolf
2018-02-26
1
-0
/
+6
*
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Clifford Wolf
2018-02-26
1
-0
/
+13
*
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
Clifford Wolf
2018-02-26
1
-0
/
+25
*
Add "SVA syntax cheat sheet" comment to verificsva.cc
Clifford Wolf
2018-02-26
1
-0
/
+34
*
Add $dlatchsr support to clk2fflogic
Clifford Wolf
2018-02-26
1
-4
/
+25
*
Small fixes and improvements in $allconst/$allseq handling
Clifford Wolf
2018-02-26
2
-16
/
+23
*
Fix opt_rmdff handling of $dlatchsr
Clifford Wolf
2018-02-26
1
-0
/
+3
*
Merge branch 'forall'
Clifford Wolf
2018-02-23
17
-98
/
+424
|
\
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*
Add smtbmc support for exist-forall problems
Clifford Wolf
2018-02-23
6
-89
/
+357
|
*
Add $allconst and $allseq cell types
Clifford Wolf
2018-02-23
11
-9
/
+67
|
/
*
Add Verific SVA support for ranges in repetition operator
Clifford Wolf
2018-02-22
1
-5
/
+26
*
Add support for SVA throughout via Verific
Clifford Wolf
2018-02-21
2
-3
/
+7
*
Add support for mockup clock signals in yosys-smtbmc vcd output
Clifford Wolf
2018-02-20
3
-6
/
+111
*
Merge pull request #507 from cr1901/msys2
Clifford Wolf
2018-02-19
1
-3
/
+3
|
\
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*
Improve msys2 flags for building abc.
William D. Jones
2018-02-19
1
-3
/
+3
|
/
*
Add support for SVA sequence concatenation ranges via verific
Clifford Wolf
2018-02-18
3
-16
/
+144
*
Add support for SVA until statements via Verific
Clifford Wolf
2018-02-18
3
-34
/
+138
*
Move Verific SVA importer to extra C++ source file
Clifford Wolf
2018-02-18
4
-1279
/
+1370
*
Merge Verific SVA preprocessor and SVA importer
Clifford Wolf
2018-02-18
1
-79
/
+44
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2018-02-16
1
-0
/
+6
|
\
|
*
Improve handling of "bus" pins in liberty front-end (some files use bus.pin.d...
Clifford Wolf
2018-02-15
1
-0
/
+6
*
|
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
Clifford Wolf
2018-02-15
2
-1
/
+35
|
/
*
Fixed yosys-config for binary distributions with Verific
Clifford Wolf
2018-02-13
1
-3
/
+11
*
Recognize stand-alone obj pattern even when it contains a slash
Clifford Wolf
2018-02-13
1
-0
/
+3
*
Fix handling of zero-length cell connections in SMT2 back-end
Clifford Wolf
2018-02-08
1
-0
/
+8
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2018-02-03
1
-0
/
+2
|
\
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*
Merge pull request #488 from azonenberg/for_clifford
Clifford Wolf
2018-02-03
1
-0
/
+2
|
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