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* genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-222-4/+10
* Merge pull request #2499 from whitequark/cxxrtl-fixeswhitequark2020-12-221-9/+10
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| * cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
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* Merge pull request #2498 from StefanBruens/Fix_opt_lutwhitequark2020-12-221-2/+4
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| * Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
* | Merge pull request #2497 from whitequark/cxxrtl-reflowwhitequark2020-12-222-446/+608
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| * cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
| * kernel: undef Tcl macros interfering with cxxrtl.whitequark2020-12-221-0/+2
| * cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
| * cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
| * cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
| * cxxrtl: fix typo.whitequark2020-12-211-2/+2
* | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-222-0/+14
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| * | Allow constant function calls in constant function argumentsZachary Snow2020-12-072-0/+14
* | | Merge pull request #2491 from zachjs/port-bind-signwhitequark2020-12-225-5/+132
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| * | | Sign extend port connections where necessaryZachary Snow2020-12-185-5/+132
* | | | Bump versionYosys Bot2020-12-221-1/+1
* | | | xilinx: Add some missing blackbox cells.Marcelina Kościelnicka2020-12-213-798/+6276
* | | | xilinx: Regenerate cells_xtra.v using Vivado 2020.2Marcelina Kościelnicka2020-12-212-42/+49
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* | | Merge pull request #2496 from whitequark/cxxrtl-fixeswhitequark2020-12-213-9/+32
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| * | | cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
| * | | cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
| * | | cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
* | | | Bump versionYosys Bot2020-12-201-1/+1
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* | | Merge pull request #2487 from whitequark/cxxrtl-outliningwhitequark2020-12-196-169/+415
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| * | | cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
| * | | cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
| * | | cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
| * | | cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
| * | | cxxrtl: implement debug information outlining.whitequark2020-12-145-71/+278
| * | | cxxrtl: rename "elision" to "inlining". NFC.whitequark2020-12-131-77/+77
| * | | cxxrtl: fix outdated comment. NFC.whitequark2020-12-131-2/+2
| * | | cxxrtl: use IdString::isPublic(). NFC.whitequark2020-12-131-4/+4
| * | | kernel: make IdString::isPublic() const.whitequark2020-12-121-1/+1
* | | | Bump versionYosys Bot2020-12-181-1/+1
* | | | xilinx: Add FDDRCPE and FDDRRSE blackbox cells.Marcelina Kościelnicka2020-12-172-0/+33
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* | | Bump versionYosys Bot2020-12-151-1/+1
* | | timinginfo: Error instead of segfault on const signals.Marcelina Kościelnicka2020-12-151-2/+2
* | | Bump versionYosys Bot2020-12-131-1/+1
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* | Merge pull request #2485 from whitequark/cxxrtl-cell-input-bufferingwhitequark2020-12-122-25/+33
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| * | cxxrtl: don't overwrite buffered inputs.whitequark2020-12-112-25/+33
* | | Bump versionYosys Bot2020-12-101-1/+1
* | | Merge pull request #2483 from YosysHQ/pmgen_nice_errorMiodrag Milanović2020-12-091-2/+6
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| * | | Return nice error in pmgen generated code, fixes #2482Miodrag Milanovic2020-12-091-2/+6
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* / / Bump versionYosys Bot2020-12-091-1/+1
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* | Merge pull request #2478 from whitequark/improve-bugpointwhitequark2020-12-082-19/+101
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| * bugpoint: add -wires option.whitequark2020-12-072-4/+39
| * bugpoint: try to remove whole processes first.whitequark2020-12-071-4/+40
| * bugpoint: accept quoted strings in -grep.whitequark2020-12-071-1/+4
| * bugpoint: add -command option.whitequark2020-12-071-13/+21
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