iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18	2	-50/+99
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\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18	1	-5/+34
\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18	1	-31/+31
\| *	Improved non-verbose ezSAT::printDIMACS() format	Clifford Wolf	2014-02-18	1	-1/+6
\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18	1	-14/+29
* \|	Progress in presentation	Clifford Wolf	2014-02-18	6	-3/+72
* \|	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	8	-8/+31
*	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	Clifford Wolf	2014-02-17	1	-5/+9
*	Added "-dump_fail_to_vcd" argument to SAT solver	Andrew Zonenberg	2014-02-17	1	-0/+114
*	Progress in presentation	Clifford Wolf	2014-02-17	3	-9/+37
*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+80
*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16	1	-2/+2
*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16	1	-0/+5
*	Progress in presentation	Clifford Wolf	2014-02-16	5	-1/+79
*	Fixed use of selection in splitnets command	Clifford Wolf	2014-02-16	1	-1/+1
*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-3/+74
*	Progress in presentation	Clifford Wolf	2014-02-16	6	-1/+114
*	Improved support for constant functions	Clifford Wolf	2014-02-16	1	-1/+50
*	Now we are in Yoys 0.2.0+ development	Clifford Wolf	2014-02-16	2	-3/+9
*	Tagging Yoys 0.2.0	Clifford Wolf	2014-02-16	2	-5/+88
*	Added != support for relational select pattern	Clifford Wolf	2014-02-16	1	-1/+7
*	Added iopadmap -bits	Clifford Wolf	2014-02-15	1	-14/+48
*	Added ff and latch support to read_liberty	Clifford Wolf	2014-02-15	1	-40/+254
*	Bugfix in expression parser of read_liberty	Clifford Wolf	2014-02-15	1	-2/+1
*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15	1	-11/+1
*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15	1	-5/+8
*	Fixed opt_const handling of double invert with non-1 output width	Clifford Wolf	2014-02-15	1	-1/+1
*	Added liberty frontend	Clifford Wolf	2014-02-15	2	-0/+362
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14	1	-1/+5
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	3	-0/+43
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	4	-49/+184
*	Added abc -keepff option	Clifford Wolf	2014-02-14	1	-5/+18
*	updated default ABC command strings	Clifford Wolf	2014-02-13	1	-4/+4
*	Updated ABC	Clifford Wolf	2014-02-13	2	-1/+24
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	4	-66/+109
*	Removed double blanks in ABC default command sequences	Clifford Wolf	2014-02-13	1	-4/+4
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-13	3	-33/+60
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\| *	Merge pull request #26 from ahmedirfan1983/btor	Clifford Wolf	2014-02-12	3	-33/+60
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\| \| *	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12	2	-6/+6
\| \| *	disabling splice command in the script	Ahmed Irfan	2014-02-11	2	-2/+6
\| \| *	register output corrected	Ahmed Irfan	2014-02-11	1	-1/+1
\| \| *	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-02-11	4	-9/+14
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\| \| * \|	added concat and slice cell translation	Ahmed Irfan	2014-02-11	3	-36/+59
* \| \| \|	Updated ABC and some related changes	Clifford Wolf	2014-02-13	3	-13/+33
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