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* Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ...Andrew Zonenberg2017-08-284-13/+13
* Merge branch 'azonenberg-recover-reduce'Clifford Wolf2017-08-282-0/+240
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| * Rename recover_reduce to extract_reduce, fix args handlingClifford Wolf2017-08-282-8/+25
| * Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azo...Clifford Wolf2017-08-282-0/+223
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| * recover_reduce: Update documentationRobert Ou2017-08-271-8/+11
| * recover_reduce: Reindent using tabsRobert Ou2017-08-271-190/+190
| * recover_reduce: Rename recover_reduce_core to recover_reduceRobert Ou2017-08-273-101/+0
| * recover_reduce: Add driver script for the $reduce_* recover featureRobert Ou2017-08-272-0/+101
| * recover_reduce_core: Finish implementing the core functionRobert Ou2017-08-271-0/+110
| * recover_reduce_core: Initial commitRobert Ou2017-08-272-0/+110
* | Further improve extract_fa passClifford Wolf2017-08-281-1/+42
* | Merge pull request #392 from azonenberg/greenpak-portfixesClifford Wolf2017-08-281-2/+2
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| * Fixed bug causing GP_SPI model to not synthesizeAndrew Zonenberg2017-08-271-2/+2
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* Don't track , ... contradictions through x/z-bitsClifford Wolf2017-08-251-1/+4
* Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_exprClifford Wolf2017-08-251-0/+72
* Merge branch 'extract_fa'Clifford Wolf2017-08-252-0/+502
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| * Further improve extract_fa (seems to be fully functional now)Clifford Wolf2017-08-251-10/+226
| * Rename "adders" to "extract_fa"Clifford Wolf2017-08-252-28/+16
| * Towards more generic "adder" function extractorClifford Wolf2017-08-231-202/+53
| * Add experimental adders passClifford Wolf2017-08-222-0/+447
* | Fix bug in write_smt2 (export logic driving hierarchical cells before exporti...Clifford Wolf2017-08-251-34/+34
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* Add hashlib support for hashing of poolsClifford Wolf2017-08-221-0/+7
* Add consteval support for $_ANDNOT_ and $_ORNOT_Clifford Wolf2017-08-221-0/+4
* Remove some dead code from fsm_mapClifford Wolf2017-08-211-3/+0
* Rename "singleton" pass to "uniquify"Clifford Wolf2017-08-203-21/+22
* More intuitive handling of "cd .." for singleton modulesClifford Wolf2017-08-191-2/+38
* Add "sim -zinit -rstlen"Clifford Wolf2017-08-181-1/+53
* Merge branch 'sim'Clifford Wolf2017-08-184-0/+848
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| * Add "sim" support for memoriesClifford Wolf2017-08-181-2/+136
| * Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-182-0/+37
| * Add support for assert/assume/cover to "sim" commandClifford Wolf2017-08-181-4/+47
| * Add writeback mode to "sim" commandClifford Wolf2017-08-171-0/+44
| * Improve "sim" commandClifford Wolf2017-08-171-54/+272
| * Add "sim" command skeletonClifford Wolf2017-08-162-0/+372
* | Merge pull request #386 from azonenberg/gpak-countersClifford Wolf2017-08-161-73/+82
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| * Fixed more issues with GreenPAK counter sim modelsAndrew Zonenberg2017-08-151-19/+23
| * Updated PGEN model to have level triggered reset (matches actual hardware beh...Andrew Zonenberg2017-08-151-4/+4
| * Fixed bug in GP_COUNTx modelAndrew Zonenberg2017-08-151-7/+12
| * Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was highAndrew Zonenberg2017-08-151-47/+47
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* Merge branch 'azonenberg-rmports'Clifford Wolf2017-08-152-0/+188
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| * Mostly coding style related fixes in rmports passClifford Wolf2017-08-151-30/+33
| * Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg...Clifford Wolf2017-08-152-0/+185
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| * rmports: Now remove ports from cell instances if we optimized them out of tha...Andrew Zonenberg2017-08-141-2/+35
| * ProcessModule is no longer virtual (why was it in the first place?)Andrew Zonenberg2017-08-141-1/+1
| * rmports now works on all modules in the design, not just the top.Andrew Zonenberg2017-08-141-4/+7
| * Updated Makefile to reflect opt_rmports being renamed to rmportsAndrew Zonenberg2017-08-141-1/+1
| * Renamed opt_rmports pass to rmportsAndrew Zonenberg2017-08-141-5/+5
| * Improved handling of constant connections in opt_rmportsAndrew Zonenberg2017-08-141-0/+2
| * Fixed handling of cell ports that aren't wiresAndrew Zonenberg2017-08-141-0/+3
| * opt_rmports: Fixed incorrect handling of multi-bit netsAndrew Zonenberg2017-08-141-12/+27
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