| Commit message (Expand) | Author | Age | Files | Lines |
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| * | | | | | | Merge pull request #1681 from YosysHQ/eddie/fix1663 | Claire Wolf | 2020-03-03 | 1 | -15/+13 |
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| | * | | | | | | verilog: instead of modifying localparam size, extend init constant expr | Eddie Hung | 2020-02-05 | 1 | -15/+13 |
| * | | | | | | | Merge pull request #1519 from YosysHQ/eddie/submod_po | Claire Wolf | 2020-03-03 | 2 | -37/+223 |
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| | * | | | | | | Merge branch 'master' into eddie/submod_po | Eddie Hung | 2020-02-01 | 219 | -5980/+12044 |
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| | * | | | | | | | Add a quick testcase for unknown modules as inout | Eddie Hung | 2019-12-09 | 1 | -2/+24 |
| | * | | | | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-02 | 1 | -1/+1 |
| * | | | | | | | | iopadmap: Look harder for already-present buffers. (#1731) | Marcelina Kościelnicka | 2020-03-02 | 2 | -16/+75 |
| * | | | | | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 43 | -1697/+3425 |
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| | * | | | | | | | | Remove RAMB{18,36}E1 from cells_xtra.py | Eddie Hung | 2020-02-27 | 1 | -2/+2 |
| | * | | | | | | | | Small fixes | Eddie Hung | 2020-02-27 | 2 | -8/+8 |
| | * | | | | | | | | Fixes for older compilers | Eddie Hung | 2020-02-27 | 2 | -2/+9 |
| | * | | | | | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" | Eddie Hung | 2020-02-27 | 1 | -3/+9 |
| | * | | | | | | | | ast: quiet down when deriving blackbox modules | Eddie Hung | 2020-02-27 | 2 | -12/+20 |
| | * | | | | | | | | abc9_ops: suppress -prep_box warning for abc9_flop | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 |
| | * | | | | | | | | ice40: add delays to SB_CARRY | Eddie Hung | 2020-02-27 | 1 | -0/+30 |
| | * | | | | | | | | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| | * | | | | | | | | Make TimingInfo::TimingInfo(SigBit) constructor explicit | Eddie Hung | 2020-02-27 | 3 | -8/+9 |
| | * | | | | | | | | TimingInfo: index by (port_name,offset) | Eddie Hung | 2020-02-27 | 2 | -12/+23 |
| | * | | | | | | | | Fix spacing | Eddie Hung | 2020-02-27 | 2 | -68/+68 |
| | * | | | | | | | | More +/ice40/cells_sim.v fixes | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | | | | | | Cleanup tests | Eddie Hung | 2020-02-27 | 2 | -1/+1 |
| | * | | | | | | | | Update bug1630.ys to use -lut 4 instead of lut file | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 |
| | * | | | | | | | | abc9_ops: still emit delay table even box has no timing | Eddie Hung | 2020-02-27 | 1 | -3/+1 |
| | * | | | | | | | | write_xaiger: add comment about arrival times of flop outputs | Eddie Hung | 2020-02-27 | 1 | -0/+1 |
| | * | | | | | | | | abc9_ops: demote lack of box timing info to warning | Eddie Hung | 2020-02-27 | 1 | -2/+4 |
| | * | | | | | | | | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 6 | -651/+530 |
| | * | | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 2 | -25/+22 |
| | * | | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 3 | -97/+65 |
| | * | | | | | | | | abc9_ops: add and use new TimingInfo struct | Eddie Hung | 2020-02-27 | 2 | -70/+214 |
| | * | | | | | | | | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 |
| | * | | | | | | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy | Eddie Hung | 2020-02-27 | 1 | -14/+12 |
| | * | | | | | | | | ice40: fix specify for inverted clocks | Eddie Hung | 2020-02-27 | 1 | -27/+27 |
| | * | | | | | | | | Fix tests by gating some specify constructs from iverilog | Eddie Hung | 2020-02-27 | 1 | -0/+16 |
| | * | | | | | | | | Update simple_abc9 tests | Eddie Hung | 2020-02-27 | 3 | -5/+8 |
| | * | | | | | | | | abc9_ops: ignore (* abc9_flop *) if not '-dff' | Eddie Hung | 2020-02-27 | 4 | -104/+114 |
| | * | | | | | | | | ice40: specify fixes | Eddie Hung | 2020-02-27 | 3 | -66/+66 |
| | * | | | | | | | | abc9_ops: sort LUT delays to be ascending | Eddie Hung | 2020-02-27 | 1 | -1/+4 |
| | * | | | | | | | | ice40: move over to specify blocks for -abc9 | Eddie Hung | 2020-02-27 | 10 | -164/+1344 |
| | * | | | | | | | | synth_ecp5: use +/abc9_model.v | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| | * | | | | | | | | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 3 | -20/+16 |
| | * | | | | | | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_} | Eddie Hung | 2020-02-27 | 2 | -0/+11 |
| | * | | | | | | | | abc9_ops: output LUT area | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| | * | | | | | | | | ecp5: remove small LUT entries | Eddie Hung | 2020-02-27 | 1 | -24/+6 |
| | * | | | | | | | | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs | Eddie Hung | 2020-02-27 | 1 | -18/+33 |
| | * | | | | | | | | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| | * | | | | | | | | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 8 | -466/+547 |
| | * | | | | | | | | ecp5: deprecate abc9_{arrival,required} and *.{lut,box} | Eddie Hung | 2020-02-27 | 7 | -86/+120 |
| | * | | | | | | | | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 3 | -347/+670 |
