| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
| | | | ||||||
| * | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -2/+3 | |
| | | | ||||||
| * | | Really fix it! | Eddie Hung | 2019-12-27 | 1 | -10/+7 | |
| | | | ||||||
| * | | write_xaiger: fix arrival times for non boxes | Eddie Hung | 2019-12-27 | 1 | -18/+25 | |
| | | | ||||||
| * | | write_xaiger to opt instead of just clean whiteboxes | Eddie Hung | 2019-12-23 | 1 | -1/+1 | |
| | | | ||||||
| * | | Cleanup xaiger, remove unnecessary complexity with inout | Eddie Hung | 2019-12-17 | 1 | -61/+20 | |
| | | | ||||||
| * | | Do not sigmap | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| | | | ||||||
| * | | Revert "Use sigmap signal" | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
| | | | | | | | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907. | |||||
| * | | Use sigmap signal | Eddie Hung | 2019-12-16 | 1 | -1/+1 | |
| | | | ||||||
| * | | Skip $inout transformation if not a PI | Eddie Hung | 2019-12-16 | 1 | -3/+5 | |
| | | | ||||||
| * | | Revert "write_xaiger: use sigmap bits more consistently" | Eddie Hung | 2019-12-16 | 1 | -4/+5 | |
| | | | | | | | | | This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110. | |||||
| * | | write_xaiger: use sigmap bits more consistently | Eddie Hung | 2019-12-16 | 1 | -5/+4 | |
| | | | ||||||
| * | | Fix writing non-whole modules, including inouts and keeps | Eddie Hung | 2019-12-06 | 1 | -90/+81 | |
| | | | ||||||
| * | | write_xaiger to support part-selected modules again | Eddie Hung | 2019-12-05 | 1 | -11/+37 | |
| | | | ||||||
| * | | Cleanup | Eddie Hung | 2019-12-03 | 1 | -11/+12 | |
| | | | ||||||
| * | | write_xaiger to consume abc9_init attribute for abc9_flops | Eddie Hung | 2019-12-03 | 1 | -34/+28 | |
| | | | ||||||
| * | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 | |
| | | | ||||||
| * | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| | | | | | | | | | This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118. | |||||
| * | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
| | | | ||||||
| * | | Fold loop | Eddie Hung | 2019-11-25 | 1 | -6/+3 | |
| | | | ||||||
| * | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-25 | 1 | -1/+1 | |
| | | | ||||||
| * | | write_xaiger back to working with whole modules only | Eddie Hung | 2019-11-22 | 1 | -5/+2 | |
| | | | ||||||
| * | | Revert "write_xaiger to not use module POs but only write outputs if driven" | Eddie Hung | 2019-11-22 | 1 | -23/+11 | |
| | | | | | | | | | This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673. | |||||
| * | | write_xaiger to not use module POs but only write outputs if driven | Eddie Hung | 2019-11-21 | 1 | -11/+23 | |
| | | | ||||||
| * | | abc9 to support async flops $_DFF_[NP][NP][01]_ | Eddie Hung | 2019-11-19 | 1 | -1/+2 | |
| | | | ||||||
| * | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -8/+8 | |
| | | | ||||||
| * | | Get rid of latch_* in write_xaiger | Eddie Hung | 2019-10-07 | 1 | -7/+1 | |
| | | | ||||||
| * | | Remove "write_xaiger -zinit" | Eddie Hung | 2019-10-07 | 1 | -16/+6 | |
| | | | ||||||
| * | | Add comment on default flop init | Eddie Hung | 2019-10-07 | 1 | -0/+1 | |
| | | | ||||||
| * | | Get rid of output_port lookup | Eddie Hung | 2019-10-07 | 1 | -14/+8 | |
| | | | ||||||
| * | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -48/+70 | |
| | | | ||||||
| * | | Error if $currQ not found | Eddie Hung | 2019-10-05 | 1 | -0/+4 | |
| | | | ||||||
| * | | Fix merge issues | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | | | ||||||
| * | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -11/+11 | |
| |\| | ||||||
| | * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -9/+9 | |
| | | | ||||||
| * | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 1 | -0/+24 | |
| | | | ||||||
| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -3/+3 | |
| | | | ||||||
| * | | Cleanup | Eddie Hung | 2019-09-30 | 1 | -100/+3 | |
| | | | ||||||
| * | | Use a cell_cache to instantiate once rather than opt_merge call | Eddie Hung | 2019-09-30 | 1 | -15/+15 | |
| | | | ||||||
| * | | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 1 | -8/+12 | |
| | | | ||||||
| * | | Use derived module | Eddie Hung | 2019-09-30 | 1 | -22/+5 | |
| | | | ||||||
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -8/+8 | |
| |\| | ||||||
| | * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -8/+8 | |
| | |\ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | |||||
| | | * | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -1/+6 | |
| | | | | ||||||
| | | * | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 1 | -1/+1 | |
| | | | | ||||||
| | | * | When two boxes connect to each other, need not be a (* keep *) | Eddie Hung | 2019-09-19 | 1 | -6/+1 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
| |\| | | ||||||
| | * | | Support binary files for backends, fixes #1407 | Miodrag Milanovic | 2019-09-28 | 1 | -1/+1 | |
| | |/ | ||||||
| * | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -62/+93 | |
| | | | ||||||
| * | | Use abc_mergeability attr for "r" extension | Eddie Hung | 2019-09-27 | 1 | -58/+66 | |
| | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |