| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add array support to btor back-end | Clifford Wolf | 2017-12-15 | 1 | -6/+169 | |
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| * | Add $anyconst/$anyseq support to btor back-end | Clifford Wolf | 2017-12-15 | 1 | -13/+51 | |
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| * | Add "write_btor -s" mode | Clifford Wolf | 2017-12-13 | 1 | -6/+50 | |
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| * | Add state initval handling to btor back-end | Clifford Wolf | 2017-12-12 | 1 | -0/+25 | |
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| * | Add btor back-end support for 'x' constants | Clifford Wolf | 2017-12-12 | 1 | -1/+54 | |
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| * | Add btor $shift/$shiftx support | Clifford Wolf | 2017-12-11 | 2 | -7/+37 | |
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| * | Fix btor back-end shift handling | Clifford Wolf | 2017-12-10 | 2 | -5/+7 | |
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| * | Add support for $pmux in btor back-end | Clifford Wolf | 2017-12-10 | 1 | -0/+23 | |
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| * | Add support for more cell types to btor back-end | Clifford Wolf | 2017-12-10 | 2 | -6/+245 | |
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| * | Fix btor concat | Clifford Wolf | 2017-12-09 | 1 | -1/+1 | |
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| * | Bugfixes in new BTOR back-end | Clifford Wolf | 2017-11-24 | 1 | -2/+3 | |
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| * | Progress in new BTOR back-end | Clifford Wolf | 2017-11-23 | 1 | -36/+97 | |
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| * | Progress in new BTOR back-end | Clifford Wolf | 2017-11-23 | 1 | -3/+95 | |
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| * | Progress in new BTOR back-end | Clifford Wolf | 2017-11-23 | 1 | -14/+72 | |
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| * | Progress with new BTOR backend | Clifford Wolf | 2017-11-23 | 1 | -8/+109 | |
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| * | Add skeleton for new BTOR back-end | Clifford Wolf | 2017-11-23 | 2 | -0/+216 | |
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| * | Remove old BTOR back-end | Clifford Wolf | 2017-11-23 | 4 | -1174/+0 | |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
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| * | Renamed opt_const to opt_expr | Clifford Wolf | 2016-03-31 | 1 | -1/+1 | |
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| * | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 | 1 | -8/+8 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -1/+1 | |
| | | | | | Smaller this time | |||||
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -2/+2 | |
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| * | Remove some very strange whitespace in btor.cc (by Larry Doolittle) | Clifford Wolf | 2015-08-05 | 1 | -7/+7 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 3 | -89/+89 | |
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| * | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 1 | -1/+1 | |
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| * | Removed "techmap -share_map" (use "-map +/filename" instead) | Clifford Wolf | 2015-04-08 | 1 | -1/+1 | |
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| * | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 | |
| | | | | corrected url | |||||
| * | Delete btor.ys | Ahmed Irfan | 2015-04-03 | 1 | -18/+0 | |
| | | | | .ys script not needed | |||||
| * | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 | |
| | | | | pmux cell is implemented | |||||
| * | separated memory next from write cell | Ahmed Irfan | 2015-04-03 | 1 | -7/+55 | |
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| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 1 | -2/+2 | |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 | |
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| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor | Ahmed Irfan | 2014-09-22 | 2 | -199/+199 | |
| |\ | | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc | |||||
| | * | Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵ | Clifford Wolf | 2014-09-01 | 1 | -1/+2 | |
| | | | | | | | | | RTLIL::SigChunk::data | |||||
| | * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 1 | -65/+65 | |
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| | * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 | |
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| | * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -11/+11 | |
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| | * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -34/+34 | |
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| | * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -1/+3 | |
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| | * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+1 | |
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| | * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 | |
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| | * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 | |
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| | * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 | |
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| | * | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 1 | -34/+34 | |
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| | * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+4 | |
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| | * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -34/+34 | |
| | | | | | | | | | | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | |||||
| | * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -34/+34 | |
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| | * | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 1 | -21/+21 | |
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| | * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -2/+2 | |
| | | | | | | | | | created interim RTLIL::SigSpec::chunks_rw() | |||||
| | * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -40/+40 | |
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index : iCE40/yosys | |
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