| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | cxxrtl: emit debug information for alias wires. | whitequark | 2020-06-08 | 1 | -3/+55 | |
| | | | | | | | | Alias wires can represent a significant chunk of the design in highly hierarchical designs; in Minerva SRAM, there are 273 member wires and 527 alias wires. Showing them in every hierarchy level significantly improves usability. | |||||
| * | cxxrtl: fix typo in comment. NFC. | whitequark | 2020-06-08 | 1 | -4/+4 | |
| | | ||||||
| * | cxxrtl: minor debug-related improvements. | whitequark | 2020-06-08 | 1 | -2/+3 | |
| | | ||||||
| * | cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. | whitequark | 2020-06-07 | 1 | -0/+2520 | |
| To avoid confusion with the C++ source files that are a part of the simulation itself and not a part of Yosys build. | ||||||
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
| aboutsummaryrefslogtreecommitdiffstats |