iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	cxxrtl: fix two buggy split_by functions.	whitequark	2020-06-09	1	-7/+9
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*	cxxrtl: ignore cell input signedness when it is irrelevant.	whitequark	2020-06-09	1	-7/+16
\| \| \| \| \| \| \| \|	Before this commit, Verilog expressions like `x && 1` would result in references to `logic_and_us` in generated CXXRTL code, which would not compile. After this commit, since cells like that actually behave the same regardless of signedness attributes, the signedness is ignored, which also reduces the template instantiation pressure.
*	cxxrtl: fix format of hdlnames.	whitequark	2020-06-08	1	-1/+1
\| \| \| \| \|	The CXXRTL code that handled the `hdlname` attribute implemented outdated semantics.
*	cxxrtl: emit debug information for constant wires.	whitequark	2020-06-08	1	-12/+27
\| \| \| \| \| \| \| \| \|	Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
*	cxxrtl: emit debug information for alias wires.	whitequark	2020-06-08	1	-3/+55
\| \| \| \| \| \| \|	Alias wires can represent a significant chunk of the design in highly hierarchical designs; in Minerva SRAM, there are 273 member wires and 527 alias wires. Showing them in every hierarchy level significantly improves usability.
*	cxxrtl: fix typo in comment. NFC.	whitequark	2020-06-08	1	-4/+4
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*	cxxrtl: minor debug-related improvements.	whitequark	2020-06-08	1	-2/+3
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*	cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.	whitequark	2020-06-07	1	-0/+2520
	To avoid confusion with the C++ source files that are a part of the simulation itself and not a part of Yosys build.