iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	cxxrtl: provide a way to perform unobtrusive power-on reset.	whitequark	2020-12-02	1	-0/+8
\| \| \| \| \| \| \| \| \| \| \|	Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API).
*	cxxrtl: expose driver kind in debug information.	whitequark	2020-09-02	1	-1/+44
\| \| \| \| \| \|	This can be useful to determine whether the wire should be a part of a design checkpoint, whether it can be used to override design state, and whether driving it may cause a conflict.
*	cxxrtl: expose port direction in debug information.	whitequark	2020-09-02	1	-0/+25
\| \| \| \| \| \|	This can be useful to distinguish e.g. a combinatorially driven wire with type `CXXRTL_VALUE` from a module input with the same type, as well as general introspection.
*	cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.	whitequark	2020-09-02	1	-1/+1
\| \| \| \| \|	Nodes driven by a constant value have type CXXRTL_VALUE and their `next` pointer set to NULL. (This is already documented.)
*	cxxrtl: fix typo. NFC.	whitequark	2020-07-14	1	-1/+1
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*	cxxrtl: expose eval() and commit() via the C API.	whitequark	2020-07-12	1	-0/+12
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*	cxxrtl: handle multipart signals.	whitequark	2020-06-11	1	-5/+25
\| \| \| \|	This avoids losing design visibility when using the `splitnets` pass.
*	cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.	whitequark	2020-06-11	1	-0/+6
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*	cxxrtl: disambiguate values/wires and their aliases in debug info.	whitequark	2020-06-10	1	-2/+9
\| \| \| \| \| \| \|	With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation).
*	cxxrtl: emit debug information for constant wires.	whitequark	2020-06-08	1	-5/+6
\| \| \| \| \| \| \| \| \|	Constant wires can represent a significant chunk of the design in generic designs or after optimization. Emitting them in VCD files significantly improves usability because gtkwave removes all traces that are not present in the VCD file after reload, and iterative development suffers if switching a varying signal to a constant disrupts the workflow.
*	cxxrtl: add a C API for driving and introspecting designs.	whitequark	2020-06-06	1	-0/+151
	Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.