iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
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*	write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.	whitequark	2020-04-09	2	-46/+78
\| \| \| \| \| \| \| \| \| \|	After this commit, if NDEBUG is not defined, out-of-bounds accesses cause assertion failures for reads and writes. If NDEBUG is defined, out-of-bounds reads return zeroes, and out-of-bounds writes are ignored. This commit also adds support for memories that start with a non-zero index (`Memory::start_offset` in RTLIL).
*	write_cxxrtl: statically schedule comb logic and localize wires.	whitequark	2020-04-09	2	-68/+368
\| \| \| \| \| \|	This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions.
*	write_cxxrtl: elide wires for results of comb cells used once.	whitequark	2020-04-09	1	-35/+359
\| \| \| \| \|	This results in massive gains in performance, equally massive reduction in compile time, and improved readability.
*	write_cxxrtl: new backend.	whitequark	2020-04-09	3	-0/+2010
	This commit adds a basic implementation that isn't very performant but implements most of the planned features.