| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -4/+4 |
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| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -0/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. | ||||
| * | Support filename rewrite in backends | Ben Widawsky | 2019-06-18 | 1 | -0/+1 |
| | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 1 | -1/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix a syntax bug in ilang backend related to process case statements | Clifford Wolf | 2019-03-14 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -4/+4 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Fixed gcc 7.2 "statement will never be executed" warning | Clifford Wolf | 2018-02-03 | 1 | -1/+1 |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -0/+7 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -0/+1 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 2 | -5/+5 |
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| * | Shorter "dump" options | Clifford Wolf | 2015-01-31 | 1 | -4/+4 |
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| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 1 | -0/+2 |
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| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 1 | -50/+24 |
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| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+2 |
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| * | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 1 | -17/+17 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+6 |
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| * | Sorting of object names in ilang backend | Clifford Wolf | 2014-09-19 | 2 | -21/+49 |
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| * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 2 | -134/+132 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 2 | -4/+8 |
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| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 1 | -0/+2 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -3/+2 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
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| * | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 1 | -2/+2 |
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| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -1/+1 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
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| * | Added "autoidx" statement to ilang file format | Clifford Wolf | 2014-07-21 | 1 | -1/+14 |
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| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 1 | -0/+1 |
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| * | Added support for dump -append | Clifford Wolf | 2014-02-04 | 1 | -3/+12 |
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| * | Updated manual/command-reference-manual.tex | Clifford Wolf | 2013-12-28 | 1 | -1/+1 |
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| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
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| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -8/+11 |
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| * | Added dump -m and -n options | Clifford Wolf | 2013-11-29 | 2 | -54/+89 |
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| * | Added support for signed parameters in ilang | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
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| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -2/+0 |
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| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -0/+1 |
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| * | Write yosys version to output files | Clifford Wolf | 2013-11-03 | 1 | -0/+1 |
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| * | Added -selected option to various backends | Clifford Wolf | 2013-09-03 | 1 | -3/+20 |
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| * | Fixed generation of newlines in "dump" output | Clifford Wolf | 2013-06-10 | 1 | -3/+4 |
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| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 2 | -13/+103 |
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| * | Added more help messages | Clifford Wolf | 2013-03-01 | 1 | -1/+11 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 3 | -0/+356 |
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index : iCE40/yosys | |
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