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* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
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* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
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* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
|\ | | | | Fixed bug in $mem cel
--  GHDL Run Time (GRT) - Wave option file top package.
--  Copyright (C) 2016 Jonas Baggett
--
--  GHDL is free software; you can redistribute it and/or modify it under
--  the terms of the GNU General Public License as published by the Free
--  Software Foundation; either version 2, or (at your option) any later
--  version.
--
--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
--  for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with GCC; see the file COPYING.  If not, write to the Free
--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
--  02111-1307, USA.
--
--  As a special exception, if other files instantiate generics from this
--  unit, or you link this unit with other files to produce an executable,
--  this unit does not by itself cause the resulting executable to be
--  covered by the GNU General Public License. This exception does not
--  however invalidate any other reasons why the executable file might be
--  covered by the GNU Public License.

-- Description: Wave option file top package.
--              Allows to select signals to be displayed on the waveform (with
--              the help of it's child units)
--              Contains common stuff for it's child units

package Grt.Wave_Opt is
   pragma Preelaborate;

   -- State :
   -- Display_All  : No signal filtering, display all
   -- Write_File   : Write in a new wave option file the signals found in the
   --                design. No signal filtering too.
   -- Display_Tree : Parse the given option file and create the tree. Display
   --                only the signals that are in the tree
   type State_Type is (Display_All, Write_File, Display_Tree);
   State : State_Type := Display_All;

   type String_Cst is access constant String;
   Value_String_Size : constant := 10;

   File_Path : String_Cst;

   type Elem_Kind_Type is (Not_Found, Pkg_Entity, Signal, Recursion);
   type Elem_Type;
   type Elem_Acc is access Elem_Type;
   type Elem_Type is record
      Expr : String_Cst;
      Lineno : Natural;
      Column : Natural;
      Level : Natural;
      Kind : Elem_Kind_Type := Not_Found;
      Parent : Elem_Acc := null;
      Next_Sibling, Next_Child : Elem_Acc := null;
   end record;

   type Tree_Index_Type is (Pkg, Entity);
   type Tree_Array is array (Tree_Index_Type) of Elem_Acc;
   Trees : Tree_Array := (others => null);
   type Sep_Array is array (Tree_Index_Type) of Character;
   Seps : constant Sep_Arr href='/cgit/iCE40/yosys/commit/backends/verilog?id=f82c978e08604c596b034fb6e74ac34c78b9364b'>Fixed AOI/OAI expr handling in verilog backend
Clifford Wolf2014-08-161-4/+4
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-161-4/+40
| | | | $_OAI4_
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
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* Refactoring of CellType classClifford Wolf2014-08-141-10/+28
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-23 21:32:11 +0000 rvative with printing decimal numbers in verilog backendClifford Wolf2014-08-021-2/+3
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* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-021-3/+19
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-40/+40
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-9/+22
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+2
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-4/+4
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-43/+43
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-43/+43
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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+29
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-3/+0
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-2/+2
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-29/+29
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-29/+29
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* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-201-17/+21
| | | | backend
* Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
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* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22
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generated by cgit v1.2.3 (git 2.25.1) at 2025-05-23 21:32:11 +0000