iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Output __const0__ and __const1__ CIs	Eddie Hung	2019-04-12	1	-7/+10
*	ci_bits and co_bits now a list, order is important for ABC	Eddie Hung	2019-04-12	1	-24/+34
*	WIP	Eddie Hung	2019-04-12	1	-14/+68
*	Add non-input bits driven by unrecognised cells as ci_bits	Eddie Hung	2019-04-10	1	-1/+1
*	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	9	-62/+305
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\| *	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
\| *	Add support for memory initialization to write_btor	Clifford Wolf	2019-03-23	1	-0/+53
\| *	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
\| *	Fix smtbmc.py handling of zero appended steps	Clifford Wolf	2019-03-14	1	-5/+5
\| *	Fix a syntax bug in ilang backend related to process case statements	Clifford Wolf	2019-03-14	1	-1/+1
\| *	Merge pull request #869 from cr1901/win-shell	Clifford Wolf	2019-03-14	1	-1/+17
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\| \| *	Install launcher executable when running yosys-smtbmc on Windows.	William D. Jones	2019-03-13	1	-1/+17
\| * \|	Improve determinism of IdString DB for similar scripts	Clifford Wolf	2019-03-11	1	-0/+4
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\| *	Fix signed $shift/$shiftx handling in write_smt2	Clifford Wolf	2019-03-09	1	-1/+2
\| *	Use SVA label in smt export if available	Clifford Wolf	2019-03-07	1	-2/+2
\| *	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-2/+1
\| *	Fix "write_edif -gndvccy"	Clifford Wolf	2019-03-01	1	-1/+1
\| *	Add "write_verilog -siminit"	Clifford Wolf	2019-02-28	1	-2/+11
\| *	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	1	-3/+3
\| *	Merge pull request #827 from ucb-bar/firrtlfixes	Clifford Wolf	2019-02-28	1	-8/+20
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\| \| *	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-8/+20
\| * \|	Fix smt2 code generation for partially initialized memowy words, fixes #831	Clifford Wolf	2019-02-28	1	-4/+11
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* \|	write_xaiger to behave for undriven/unused inouts	Eddie Hung	2019-02-26	1	-23/+25
* \|	write_xaiger duplicate inout port into out port with $inout.out suffix	Eddie Hung	2019-02-25	1	-3/+26
* \|	Cleanup abc9 code	Eddie Hung	2019-02-25	1	-13/+8
* \|	write_xaiger to write __dummy_o__ for -symbols too	Eddie Hung	2019-02-21	1	-12/+11
* \|	Add attribution	Eddie Hung	2019-02-21	1	-0/+1
* \|	write_xaiger to use original bit for co, not sigmap()-ed bit	Eddie Hung	2019-02-21	1	-3/+6
* \|	Remove swap file	Eddie Hung	2019-02-20	1	-0/+0
* \|	write_aiger: fix CI/CO and symbols	Eddie Hung	2019-02-20	2	-7/+13
* \|	write_xaiger to not write latches, CO/PO fixes	Eddie Hung	2019-02-20	1	-17/+26
* \|	Merge branch 'master' into xaig	Eddie Hung	2019-02-19	2	-66/+218
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\| *	Instead of INIT param on cells, use initial statement with hier ref as	Eddie Hung	2019-02-17	1	-18/+13
\| *	Merge https://github.com/YosysHQ/yosys into dff_init	Eddie Hung	2019-02-17	2	-86/+246
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\| \| *	Removed unused variables, functions.	Jim Lawson	2019-02-15	1	-20/+0
\| \| *	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-48/+225
* \| \|	Cleanup	Eddie Hung	2019-02-16	1	-4/+5
* \| \|	Cleanup	Eddie Hung	2019-02-16	1	-2/+1
* \| \|	write_xaiger to support non-bit cell connections, and cope with COs for -O	Eddie Hung	2019-02-16	1	-13/+15
* \| \|	write_aiger -O to write dummy output as __dummy_o__	Eddie Hung	2019-02-16	1	-2/+5
* \| \|	Tidy up write_xaiger	Eddie Hung	2019-02-16	1	-8/+6
* \| \|	write_aiger() to perform CI/CO post-processing and fix symbols	Eddie Hung	2019-02-16	1	-7/+17
* \| \|	Fixes needed for DFF circuits	Eddie Hung	2019-02-15	1	-4/+3
* \| \|	write_xaiger to cope with unknown cells by transforming them to CI/CO	Eddie Hung	2019-02-15	1	-6/+44
* \| \|	More cleanup	Eddie Hung	2019-02-14	1	-15/+6
* \| \|	More cleanup of write_xaiger	Eddie Hung	2019-02-14	1	-73/+1
* \| \|	Get rid of formal stuff from xaiger backend	Eddie Hung	2019-02-14	1	-58/+0
* \| \|	Merge remote-tracking branch 'origin/read_aiger' into xaig	Eddie Hung	2019-02-13	1	-1/+1
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\| * \|	Remove check for cell->name[0] == '$'	Eddie Hung	2019-02-06	1	-1/+1
* \| \|	Merge https://github.com/YosysHQ/yosys into xaig	Eddie Hung	2019-02-13	1	-38/+41
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