iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Use hex addresses in smtbmc vcd mem traces	Clifford Wolf	2017-02-28	1	-1/+1
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*	Add smtbmc support for memory vcd dumping	Clifford Wolf	2017-02-26	1	-0/+98
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*	Fix extra newline bug in write_smt2	Clifford Wolf	2017-02-26	1	-1/+1
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*	Fix bug in smtio unroll code	Clifford Wolf	2017-02-26	1	-3/+2
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*	Fix assert checking in "yosys-smtbmc -c --append"	Clifford Wolf	2017-02-26	1	-1/+1
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*	Improve (and fix for stbv mode) SMT2 memory API	Clifford Wolf	2017-02-26	3	-47/+51
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*	Add support for "yosys-smtbmc -c --append"	Clifford Wolf	2017-02-25	1	-1/+13
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*	Improve "write_edif" help message	Clifford Wolf	2017-02-25	1	-7/+2
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*	Move EdifNames out of double-private namespace	Clifford Wolf	2017-02-25	1	-48/+45
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*	Clean up edif code, swap bit indexing of "upto" ports	Clifford Wolf	2017-02-25	1	-17/+35
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*	Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master	Clifford Wolf	2017-02-25	1	-6/+46
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\| *	Did as you requested, /but/...	Johann Klammer	2017-02-24	1	-45/+29
\| \| \| \| \| \| \| \|	Now the nets are wired in reverse again because the netlister still uses zero-based indices.
\| *	add options for edif flavors	Johann Klammer	2017-02-23	1	-4/+60
\| \| \| \| \| \| \| \| \| \| \| \|	to force renames on wide ports to choose array delimiters *to choose up or downwards indices
* \|	Add $live and $fair support to AIGER back-end.	Clifford Wolf	2017-02-25	1	-8/+104
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* \|	Add "write_smt2 -stbv"	Clifford Wolf	2017-02-24	3	-49/+179
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* \|	Add SMT2 statebv mode (inactive for now)	Clifford Wolf	2017-02-24	1	-20/+47
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*	Add "yosys-smtbmc -S <opt>"	Clifford Wolf	2017-02-19	1	-7/+18
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*	Add warning about x/z bits left unconnected in EDIF output	Clifford Wolf	2017-02-14	1	-2/+5
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*	More progress on Firrtl backend.	Adam Izraelevitz	2017-02-13	3	-27/+181
\| \| \| \| \|	Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
*	Add assert check in "yosys-smtbmc -c"	Clifford Wolf	2017-02-04	1	-7/+28
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*	Improve yosys-smtbmc cover() support	Clifford Wolf	2017-02-04	1	-5/+19
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*	Partially implement cover() support in yosys-smtbmc	Clifford Wolf	2017-02-04	3	-4/+97
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*	Further improve cover() support	Clifford Wolf	2017-02-04	1	-3/+5
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*	Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support	Clifford Wolf	2017-01-30	1	-5/+14
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*	Add "yosys-smtbmc --aig-noheader" and AIGER mem init support	Clifford Wolf	2017-01-28	2	-8/+55
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*	Fix $initstate handling bug in yosys-smtbmc	Clifford Wolf	2017-01-11	1	-0/+2
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*	Implicitly set "yosys-smtbmc --noprogress" on windows	Clifford Wolf	2017-01-04	1	-3/+4
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*	Fixed "yosys-smtbmc --noprogress"	Clifford Wolf	2017-01-04	1	-1/+1
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*	Handle "always 1" like "always -1" in .smtc files	Clifford Wolf	2017-01-02	1	-7/+5
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*	Improved write_json help message	Clifford Wolf	2016-12-29	1	-0/+4
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*	Added $anyconst support to AIGER back-end	Clifford Wolf	2016-12-11	1	-0/+7
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*	Added $assert/$assume support to AIGER back-end	Clifford Wolf	2016-12-03	1	-10/+51
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*	Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig	Clifford Wolf	2016-12-03	1	-2/+15
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*	Added "yosys-smtbmc --aig"	Clifford Wolf	2016-12-01	1	-6/+127
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*	Added support for partially initialized regs to smt2 back-end	Clifford Wolf	2016-12-01	1	-3/+15
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*	Added "write_aiger -zinit -symbols -vmap"	Clifford Wolf	2016-12-01	1	-30/+139
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*	Added "write_aiger" command	Clifford Wolf	2016-11-30	2	-0/+398
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*	Bugfix in smt2 back-end for pure checker modules	Clifford Wolf	2016-11-28	1	-0/+4
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*	Removed shebang line from smtio.py, fixes #279	Clifford Wolf	2016-11-27	1	-1/+0
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*	Added wire start_offset and upto handling BLIF back-end	Clifford Wolf	2016-11-23	1	-1/+1
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*	Added "yosys-smtbmc --append"	Clifford Wolf	2016-11-22	1	-2/+20
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*	Bugfix: include assign to write-mask	Adam Izraelevitz	2016-11-18	1	-0/+1
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*	More progress in FIRRTL back-end	Clifford Wolf	2016-11-18	3	-4/+121
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*	Progress in FIRRTL back-end	Clifford Wolf	2016-11-18	4	-5/+55
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*	Added first draft of FIRRTL back-end	Clifford Wolf	2016-11-17	2	-0/+353
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*	Cleanups and fixed in write_verilog regarding reg init	Clifford Wolf	2016-11-16	1	-15/+61
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*	Added hex constant support to write_verilog	Clifford Wolf	2016-11-03	1	-4/+62
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*	Adde "write_verilog -renameprefix -v"	Clifford Wolf	2016-11-01	1	-5/+23
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*	Added avail params to ilang format, check module params in 'hierarchy -check'	Clifford Wolf	2016-10-22	1	-0/+7
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*	Ignore L_pi nets in "yosys-smtbmc --cex"	Clifford Wolf	2016-10-18	1	-2/+5
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