| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add "yosys-smtbmc --presat" | Clifford Wolf | 2017-07-07 | 1 | -3/+23 | |
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| * | Fix generation of multiple outputs for same AIG node in write_aiger | Clifford Wolf | 2017-07-05 | 1 | -13/+30 | |
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| * | Add write_table command | Clifford Wolf | 2017-07-05 | 2 | -0/+123 | |
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| * | Remove unneeded delays in smtbmc vlogtb | Clifford Wolf | 2017-07-03 | 1 | -1/+1 | |
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| * | Include output ports with constant driver in AIGER output | Clifford Wolf | 2017-07-03 | 1 | -2/+18 | |
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| * | Add "yosys-smtbmc --vlogtb-top" | Clifford Wolf | 2017-07-01 | 1 | -15/+32 | |
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| * | Fix smtbmc vlogtb bug in $anyseq handling | Clifford Wolf | 2017-07-01 | 1 | -3/+3 | |
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| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵ | Clifford Wolf | 2017-06-07 | 3 | -4/+53 | |
| | | | | | const reg" | |||||
| * | Fix AIGER back-end for multiple symbols per input/latch/output/property | Clifford Wolf | 2017-05-30 | 1 | -8/+20 | |
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| * | Improve write_aiger handling of unconnected nets and constants | Clifford Wolf | 2017-05-28 | 1 | -7/+61 | |
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| * | Change default smt2 solver to yices (Yices 2 has switched its license to GPL) | Clifford Wolf | 2017-05-27 | 1 | -4/+4 | |
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| * | Add workaround for CBMC bug to SimpleC back-end | Clifford Wolf | 2017-05-17 | 1 | -1/+3 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 5 | -14/+36 | |
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| * | Add <modname>_init() function generator to simpleC back-end | Clifford Wolf | 2017-05-16 | 2 | -88/+152 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-16 | 1 | -1/+1 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-15 | 1 | -42/+44 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-14 | 3 | -3/+49 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-13 | 1 | -25/+60 | |
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| * | Improve simplec back-end | Clifford Wolf | 2017-05-12 | 3 | -12/+78 | |
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| * | Added support for more gate types to simplec back-end | Clifford Wolf | 2017-05-12 | 1 | -1/+88 | |
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| * | Add first draft of simple C back-end | Clifford Wolf | 2017-05-12 | 6 | -0/+623 | |
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| * | Fix boolector support in yosys-smtbmc | Clifford Wolf | 2017-05-08 | 1 | -18/+18 | |
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| * | Add "write_smt2 -stdt" mode | Clifford Wolf | 2017-03-20 | 2 | -37/+84 | |
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| * | Add generation of logic cells to EDIF back-end runtest.py | Clifford Wolf | 2017-03-19 | 1 | -2/+6 | |
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| * | Fix EDIF: portRef member 0 is always the MSB bit | Clifford Wolf | 2017-03-19 | 2 | -13/+14 | |
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| * | Add simple EDIF test case generator and checker | Clifford Wolf | 2017-03-18 | 1 | -0/+113 | |
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| * | Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg | Clifford Wolf | 2017-03-04 | 2 | -33/+87 | |
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| * | Add write_aiger $anyseq support | Clifford Wolf | 2017-03-02 | 1 | -0/+7 | |
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| * | Use hex addresses in smtbmc vcd mem traces | Clifford Wolf | 2017-02-28 | 1 | -1/+1 | |
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| * | Add smtbmc support for memory vcd dumping | Clifford Wolf | 2017-02-26 | 1 | -0/+98 | |
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| * | Fix extra newline bug in write_smt2 | Clifford Wolf | 2017-02-26 | 1 | -1/+1 | |
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| * | Fix bug in smtio unroll code | Clifford Wolf | 2017-02-26 | 1 | -3/+2 | |
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| * | Fix assert checking in "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-26 | 1 | -1/+1 | |
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| * | Improve (and fix for stbv mode) SMT2 memory API | Clifford Wolf | 2017-02-26 | 3 | -47/+51 | |
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| * | Add support for "yosys-smtbmc -c --append" | Clifford Wolf | 2017-02-25 | 1 | -1/+13 | |
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| * | Improve "write_edif" help message | Clifford Wolf | 2017-02-25 | 1 | -7/+2 | |
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| * | Move EdifNames out of double-private namespace | Clifford Wolf | 2017-02-25 | 1 | -48/+45 | |
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| * | Clean up edif code, swap bit indexing of "upto" ports | Clifford Wolf | 2017-02-25 | 1 | -17/+35 | |
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| * | Merge branch 'master' of https://github.com/klammerj/yosys into klammerj-master | Clifford Wolf | 2017-02-25 | 1 | -6/+46 | |
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| | * | Did as you requested, /but/... | Johann Klammer | 2017-02-24 | 1 | -45/+29 | |
| | | | | | | | | | Now the nets are wired in reverse again because the netlister still uses zero-based indices. | |||||
| | * | add options for edif flavors | Johann Klammer | 2017-02-23 | 1 | -4/+60 | |
| | | | | | | | | | | | | | *to force renames on wide ports *to choose array delimiters *to choose up or downwards indices | |||||
| * | | Add $live and $fair support to AIGER back-end. | Clifford Wolf | 2017-02-25 | 1 | -8/+104 | |
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| * | | Add "write_smt2 -stbv" | Clifford Wolf | 2017-02-24 | 3 | -49/+179 | |
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| * | | Add SMT2 statebv mode (inactive for now) | Clifford Wolf | 2017-02-24 | 1 | -20/+47 | |
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| * | Add "yosys-smtbmc -S <opt>" | Clifford Wolf | 2017-02-19 | 1 | -7/+18 | |
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| * | Add warning about x/z bits left unconnected in EDIF output | Clifford Wolf | 2017-02-14 | 1 | -2/+5 | |
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| * | More progress on Firrtl backend. | Adam Izraelevitz | 2017-02-13 | 3 | -27/+181 | |
| | | | | | | Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design. | |||||
| * | Add assert check in "yosys-smtbmc -c" | Clifford Wolf | 2017-02-04 | 1 | -7/+28 | |
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| * | Improve yosys-smtbmc cover() support | Clifford Wolf | 2017-02-04 | 1 | -5/+19 | |
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| * | Partially implement cover() support in yosys-smtbmc | Clifford Wolf | 2017-02-04 | 3 | -4/+97 | |
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index : iCE40/yosys | |
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