iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	More explicit integer output in verilog backend	Clifford Wolf	2013-08-22	1	-2/+2
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*	Added correct encoding of identifiers in EDIF backend	Clifford Wolf	2013-08-22	1	-13/+61
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*	Added edif backend (still under construction)	Clifford Wolf	2013-08-22	2	-0/+202
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*	Fixed generation of newlines in "dump" output	Clifford Wolf	2013-06-10	1	-3/+4
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*	Added "dump" command (part ilang backend)	Clifford Wolf	2013-06-02	2	-13/+103
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-6/+18
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*	Added -notypes option to intersynth backend	Clifford Wolf	2013-03-24	1	-7/+18
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*	Fixed gcc build (intersynth backend)	Clifford Wolf	2013-03-23	1	-14/+14
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*	Various improvements in intersynth backend	Clifford Wolf	2013-03-23	1	-9/+56
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*	Added intersynth backend	Clifford Wolf	2013-03-23	2	-0/+141
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*	Avoid verilog-2k in verilog backend	Clifford Wolf	2013-03-21	1	-0/+17
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*	More support code for $sr cells	Clifford Wolf	2013-03-14	1	-1/+29
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*	Fixed a gcc compiler warning [-Wparentheses]	Clifford Wolf	2013-03-03	1	-1/+2
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*	Added more help messages	Clifford Wolf	2013-03-01	3	-3/+59
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*	initial import	Clifford Wolf	2013-01-05	8	-0/+1615