| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 | |
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| | * | | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 1 | -4/+41 | |
| | |/ / | | | | | | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting). | |||||
| * | | | Remove topo sort no-loop assertion, with test | Eddie Hung | 2019-04-24 | 1 | -13/+0 | |
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| * | | | Fix abc9 with (* keep *) wires | Eddie Hung | 2019-04-23 | 1 | -6/+14 | |
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| * | | Temporarily remove 'r' extension | Eddie Hung | 2019-04-22 | 1 | -77/+7 | |
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| * | | Allow POs to be PIs in XAIG | Eddie Hung | 2019-04-22 | 1 | -7/+4 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -0/+8 | |
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| | * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -1/+1 | |
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| | * | Merge pull request #943 from YosysHQ/clifford/whitebox | Clifford Wolf | 2019-04-20 | 8 | -12/+12 | |
| | |\ | | | | | | | [WIP] Add "whitebox" attribute, add "read_verilog -wb" | |||||
| | | * | Revert "write_json to not write contents (cells/wires) of whiteboxes" | Eddie Hung | 2019-04-18 | 1 | -59/+56 | |
| | | | | | | | | | | | | | This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4. | |||||
| | | * | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 | |
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| | * | | Change "ne" to "neq" in btor2 output | Clifford Wolf | 2019-04-19 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | we need to do this because they changed the parser: https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Fixes for simple_abc9 tests | Eddie Hung | 2019-04-19 | 1 | -4/+8 | |
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| * | | | Do not assume inst_module is always present | Eddie Hung | 2019-04-19 | 1 | -12/+9 | |
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| * | | | ignore_boxes -> holes_mode | Eddie Hung | 2019-04-19 | 1 | -6/+5 | |
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| * | | | Add flop support for write_xaiger | Eddie Hung | 2019-04-18 | 1 | -11/+83 | |
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| * | | | Spelling | Eddie Hung | 2019-04-18 | 1 | -1/+1 | |
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| * | | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 1 | -29/+31 | |
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| * | | | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 | |
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| * | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 8 | -12/+12 | |
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| | * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 8 | -12/+12 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix $anyseq warning and cleanup | Eddie Hung | 2019-04-17 | 1 | -16/+7 | |
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| * | | Cope with inout ports | Eddie Hung | 2019-04-17 | 1 | -1/+15 | |
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| * | | Stop topological sort at abc_flop_q | Eddie Hung | 2019-04-17 | 1 | -7/+13 | |
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| * | | Remove init* from xaiger, also topo-sort cells for box flow | Eddie Hung | 2019-04-17 | 1 | -95/+157 | |
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| * | | Optimise | Eddie Hung | 2019-04-16 | 1 | -4/+3 | |
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| * | | CIs before PIs; also sort each cell's connections before iterating | Eddie Hung | 2019-04-16 | 1 | -5/+7 | |
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| * | | Port from xc7mux branch | Eddie Hung | 2019-04-16 | 1 | -37/+109 | |
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| * | | Output __const0__ and __const1__ CIs | Eddie Hung | 2019-04-12 | 1 | -7/+10 | |
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| * | | ci_bits and co_bits now a list, order is important for ABC | Eddie Hung | 2019-04-12 | 1 | -24/+34 | |
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| * | | WIP | Eddie Hung | 2019-04-12 | 1 | -14/+68 | |
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| * | | Add non-input bits driven by unrecognised cells as ci_bits | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 9 | -62/+305 | |
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| | * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 | |
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| | * | Add support for memory initialization to write_btor | Clifford Wolf | 2019-03-23 | 1 | -0/+53 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix BTOR output tags syntax in writye_btor | Clifford Wolf | 2019-03-23 | 1 | -2/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix smtbmc.py handling of zero appended steps | Clifford Wolf | 2019-03-14 | 1 | -5/+5 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix a syntax bug in ilang backend related to process case statements | Clifford Wolf | 2019-03-14 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Merge pull request #869 from cr1901/win-shell | Clifford Wolf | 2019-03-14 | 1 | -1/+17 | |
| | |\ | | | | | | | Install launcher executable when running yosys-smtbmc on Windows. | |||||
| | | * | Install launcher executable when running yosys-smtbmc on Windows. | William D. Jones | 2019-03-13 | 1 | -1/+17 | |
| | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net> | |||||
| | * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+4 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Fix signed $shift/$shiftx handling in write_smt2 | Clifford Wolf | 2019-03-09 | 1 | -1/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Use SVA label in smt export if available | Clifford Wolf | 2019-03-07 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails | Jim Lawson | 2019-03-04 | 1 | -2/+1 | |
| | | | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value". | |||||
| | * | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -2/+11 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 1 | -3/+3 | |
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| | * | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 1 | -8/+20 | |
| | |\ | | | | | | | Fix FIRRTL to Verilog process instance subfield assignment. | |||||
| | | * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 1 | -8/+20 | |
| | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | |||||
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index : iCE40/yosys | |
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