| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Documentation for JSON format, added attributes | Clifford Wolf | 2015-03-06 | 1 | -16/+156 | |
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| * | | Json bugfix | Clifford Wolf | 2015-03-03 | 1 | -1/+1 | |
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| * | | Json backend improvements | Clifford Wolf | 2015-03-03 | 1 | -4/+12 | |
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| * | | Added write_blif -attr | Clifford Wolf | 2015-03-02 | 1 | -18/+33 | |
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| * | | Added JSON backend | Clifford Wolf | 2015-03-02 | 2 | -0/+262 | |
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| * | | Added $assume support to write_smt2 | Clifford Wolf | 2015-02-26 | 1 | -4/+19 | |
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| * | | Minor "write_smt2" help msg change | Clifford Wolf | 2015-02-22 | 1 | -1/+1 | |
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| * | | Added "<mod>_a" and "<mod>_i" to write_smt2 output | Clifford Wolf | 2015-02-22 | 1 | -23/+149 | |
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| * | | Fixed "write_verilog -attr2comment" handling of "*/" in strings | Clifford Wolf | 2015-02-13 | 1 | -2/+4 | |
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| * | Added EDIF backend support for multi-bit cell ports | Clifford Wolf | 2015-02-01 | 1 | -11/+10 | |
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| * | Shorter "dump" options | Clifford Wolf | 2015-01-31 | 1 | -4/+4 | |
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| * | Added ENABLE_NDEBUG makefile options | Clifford Wolf | 2015-01-24 | 2 | -2/+4 | |
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| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 2 | -50/+26 | |
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| * | Cosmetic changes in verilog output format | Clifford Wolf | 2015-01-02 | 1 | -5/+10 | |
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| * | Fixed memory->start_offset handling | Clifford Wolf | 2015-01-01 | 1 | -0/+2 | |
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| * | Replaced std::unordered_map as implementation for Yosys::dict | Clifford Wolf | 2014-12-26 | 2 | -42/+42 | |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 | |
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| * | Various fixes and improvements in "write_smt2 -bv" | Clifford Wolf | 2014-12-25 | 3 | -11/+43 | |
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| * | Various fixes and improvements in write_smt2 | Clifford Wolf | 2014-12-25 | 2 | -32/+88 | |
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| * | Added support for most BV cell types to write_smt2 | Clifford Wolf | 2014-12-25 | 1 | -14/+221 | |
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| * | Added "write_smt2 -bv" and other write_smt2 improvements | Clifford Wolf | 2014-12-25 | 1 | -172/+153 | |
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| * | Added write_smt2 (only gate level logic supported so far) | Clifford Wolf | 2014-12-24 | 2 | -0/+353 | |
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| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 | |
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| * | Added $dffe support to write_verilog | Clifford Wolf | 2014-12-20 | 1 | -3/+14 | |
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| * | Fixed another bug in write_blif handling of $lut cells | Clifford Wolf | 2014-12-19 | 1 | -1/+1 | |
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| * | Fixed writing of $lut cells in BLIF backend | Clifford Wolf | 2014-12-17 | 1 | -7/+7 | |
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| * | Added "write_blif -undef" and support for special "-" true/false/undef type | Clifford Wolf | 2014-12-14 | 1 | -13/+33 | |
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| * | Added "write_blif -blackbox" | Clifford Wolf | 2014-12-14 | 1 | -2/+16 | |
| | | | | | | based on code by Eddie Hung from https://github.com/eddiehung/yosys/commit/1e481661cb4a4 | |||||
| * | Added "blif -unbuf" feature | Clifford Wolf | 2014-12-14 | 1 | -0/+19 | |
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| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -1/+1 | |
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| * | Fixed generation of temp names in verilog backend | Clifford Wolf | 2014-11-07 | 1 | -4/+5 | |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 2 | -2/+2 | |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 8 | -42/+28 | |
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| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor | Ahmed Irfan | 2014-09-22 | 12 | -1284/+1139 | |
| |\ | | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc | |||||
| | * | Sorting of object names in ilang backend | Clifford Wolf | 2014-09-19 | 2 | -21/+49 | |
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| | * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 1 | -1/+2 | |
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| | * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 | |
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| | * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -1/+0 | |
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| | * | Using $pos models for $bu0 | Clifford Wolf | 2014-09-03 | 1 | -16/+1 | |
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| | * | Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵ | Clifford Wolf | 2014-09-01 | 1 | -1/+2 | |
| | | | | | | | | | RTLIL::SigChunk::data | |||||
| | * | Changed frontend-api from FILE to std::istream | Clifford Wolf | 2014-08-23 | 1 | -4/+4 | |
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| | * | Changed backend-api from FILE to std::ostream | Clifford Wolf | 2014-08-23 | 9 | -582/+579 | |
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| | * | Fixed AOI/OAI expr handling in verilog backend | Clifford Wolf | 2014-08-16 | 1 | -4/+4 | |
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| | * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵ | Clifford Wolf | 2014-08-16 | 1 | -4/+40 | |
| | | | | | | | | | $_OAI4_ | |||||
| | * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 1 | -2/+2 | |
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| | * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 2 | -2/+2 | |
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| | * | Refactoring of CellType class | Clifford Wolf | 2014-08-14 | 1 | -10/+28 | |
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| | * | Be more conservative with printing decimal numbers in verilog backend | Clifford Wolf | 2014-08-02 | 1 | -2/+3 | |
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| | * | Improved verilog output for ordinary $mux cells | Clifford Wolf | 2014-08-02 | 1 | -3/+19 | |
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| | * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 4 | -5/+5 | |
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index : iCE40/yosys | |
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