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* pass jny: added some todo comments about things that need to be done before ↵Aki Van Ness2022-04-081-0/+5
| | | | a proper merge, but it should be enough for the PoC at the moment
* pass jny: changed the constructor initializers to use parens rather than ↵Aki Van Ness2022-04-081-2/+2
| | | | curly-braces to hopefully make GCC 4.8 happy
* pass jny: fixed the string escape method to be less jank and more properAki Van Ness2022-04-081-21/+58
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* pass jny: fixed the signed output for param value outputAki Van Ness2022-04-081-1/+1
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* pass jny: added connection outputAki Van Ness2022-04-081-4/+88
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* pass jny: added filter options for including connections, attributes, and ↵Aki Van Ness2022-04-081-25/+125
| | | | properties
* pass jny: large chunk of refactoring to make the JSON output more pretty and ↵Aki Van Ness2022-04-081-75/+89
| | | | the internals less of a spaghetti nightmare
* metadata -> jny: migrated to the proper name for the passAki Van Ness2022-04-083-21/+19
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* pass metadata: added the machinery to write param and attributesAki Van Ness2022-04-081-8/+27
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* pass metadata: removed superfluous `stringf` callsAki Van Ness2022-04-081-37/+40
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* pass metadata: some more rough work on dumping the parameters and attributesAki Van Ness2022-04-081-6/+6
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* pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happyAki Van Ness2022-04-081-1/+1
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* pass metadata: added the output of parameters,Aki Van Ness2022-04-081-7/+35
| | | | it's kinda dumb at the moment and needs parsing based on type but it's a start
* pass metadata: fixed some of the output formattingAki Van Ness2022-04-081-0/+3
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* pass metadata: initial commit of the metadata pass for exporting design ↵Aki Van Ness2022-04-082-0/+277
| | | | metadata for yosys assisted tooling
* smtbmc: fix bmc with no assertionsJannis Harder2022-03-291-0/+2
| | | | this was broken by the `--keep-going` changes
* Merge pull request #3253 from jix/smtbmc-nodeepcopyJannis Harder2022-03-281-6/+6
|\ | | | | smtbmc: Avoid unnecessary deep copies during unrolling
| * smtbmc: Avoid unnecessary deep copies during unrollingJannis Harder2022-03-281-6/+6
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* | Merge pull request #3247 from jix/smtbmc-keepgoingJannis Harder2022-03-281-50/+143
|\ \ | |/ |/| smtbmc `--keep-going`
| * yosys-smtbmc: Option to keep going after failed assertions in BMC modeJannis Harder2022-03-241-48/+141
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| * yosys-smtbmc: Fix typo in help text, remove trailing whitespaceJannis Harder2022-03-241-2/+2
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* | Add -no-startoffset option to write_aigerMiodrag Milanovic2022-03-251-8/+17
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* | ignore # comment linesN. Engelhardt2022-03-241-1/+1
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* Merge pull request #3226 from YosysHQ/micko/btor2witnessMiodrag Milanović2022-03-111-2/+2
|\ | | | | Sim support for btor2 witness files
| * Fix handling of some formal cells in btor back-endClaire Xenia Wolf2022-03-111-6/+2
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * handle state names of $anyconst and $anyseqMiodrag Milanovic2022-03-111-1/+5
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* | Merge pull request #3210 from rqou/json-signedMiodrag Milanović2022-03-071-0/+2
|\ \ | |/ |/| json: Add help message for `signed` field
| * json: Add help message for `signed` fieldR2022-02-211-0/+2
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* | Merge pull request #3186 from nakengelhardt/smtbmc_sby_print_idMiodrag Milanović2022-03-042-4/+12
|\ \ | | | | | | add argument for printing cell names in yosys-smtbmc
| * | print cell name for properties in yosys-smtbmcN. Engelhardt2022-02-222-4/+12
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* | Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-041-1/+16
|\ \ | | | | | | fix handling of escaped chars in json backend and frontend (mostly)
| * | fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-181-1/+16
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* / Add a bit of flexibilty re trace length when processing aiger witnesses in ↵Claire Xenia Wolf2022-02-111-1/+4
|/ | | | | | smtbmc.py Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* verilog backend: Emit a `wire` for ports as well.Marcelina Kościelnicka2022-01-311-1/+1
| | | | Fixes #3177.
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-287-2/+77
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* cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
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* cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
| | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network>
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-121-0/+2
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
|\ | | | | cxxrtl: preserve interior memory pointers across reset
| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | | | | | This makes the depth properly immutable.
* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
| | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing.
* | write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
|/ | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.
* sta: very crude static timing analysis passLofty2021-11-251-15/+16
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
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* Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
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* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-024-4/+19
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-43/+70
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
| | | | | | | backends/protobuf/protobuf.cc depends on the source and header files generated by protoc, but this dependency wasn't explicitly declared. Add a rule to the Makefile to fix intermittent build failures when the protobuf header/source file isn't built before protobuf.cc.
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