iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
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*	Only use sha1 checksums for names of parametric modules when the verbose ↵	Clifford Wolf	2013-04-26	1	-9/+20
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+15
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+9
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-2/+18
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-2/+6
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-0/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+859