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* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-5/+13
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-301-7/+7
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+2
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* Preserve string parametersClifford Wolf2017-02-231-2/+8
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-2/+7
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-4/+2
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* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-2/+7
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* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-061-0/+1
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* Removed $predict againClifford Wolf2016-08-281-1/+0
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* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
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* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-271-5/+16
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
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* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+1
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* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
| | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+12
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* Include <cmath> in yosys.hClifford Wolf2016-05-081-9/+0
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-211-1/+10
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* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
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* Fixed segfault in AstNode::asRealClifford Wolf2015-09-251-1/+1
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* Fixed AstNode::mkconst_bits() segfault on zero-sized constantClifford Wolf2015-09-241-1/+1
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* Another block of spelling fixesLarry Doolittle2015-08-141-4/+4
| | | | Smaller this time
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Added non-std verilog assume() statementClifford Wolf2015-02-261-0/+1
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* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-2/+6
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* Creating $meminit cells in verilog front-endClifford Wolf2015-02-141-1/+2
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* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
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* dict/pool changes in astClifford Wolf2014-12-291-0/+4
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* Changed more code to dict<> and pool<>Clifford Wolf2014-12-281-1/+1
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-251-0/+2
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* minor indenting correctionsClifford Wolf2014-10-191-2/+2
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* Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-191-0/+5
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* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-2/+2
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-221-0/+4
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* Added AstNode::asInt()Clifford Wolf2014-08-211-1/+22
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* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-211-0/+1
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* Added support for global tasks and functionsClifford Wolf2014-08-211-12/+26
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* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-181-0/+8
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* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-171-1/+1
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* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
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* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-141-2/+1
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* Added module->portsClifford Wolf2014-08-141-0/+1
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* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-0/+7
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-021-2/+2
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* Replaced sha1 implementationClifford Wolf2014-08-011-27/+2
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-5/+5
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+5
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