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* Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-2/+0
| | | | Fixes #1819, #1820.
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-211-0/+5
|\ | | | | Improved rewrite code for writing to bit slice
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+5
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-34/+34
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* kernel: use more ID::*Eddie Hung2020-04-021-6/+6
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-33/+39
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-33/+39
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* | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* / Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-32/+14
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-32/+14
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-11/+19
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* add attributes for enumerated values in ilangJeff Wang2020-02-171-0/+1
| | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
* partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-3/+20
| | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-141-0/+3
|\ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix for svinterfacesEddie Hung2019-09-301-2/+8
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* | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-301-32/+50
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* Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵Clifford Wolf2019-09-201-18/+29
| | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove newlineEddie Hung2019-08-291-1/+0
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* Restore non-deferred code, deferred case to ignore non constant attrEddie Hung2019-08-291-5/+12
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* read_verilog -defer should still populate module attributesEddie Hung2019-08-281-5/+6
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* handle real values when deriving ast modulesJakob Wenzel2019-08-191-1/+4
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* Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-121-1/+1
| | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-101-1/+1
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* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-101-9/+9
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-071-2/+2
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| * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-7/+7
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* | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-1/+1
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* initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
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* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-2/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+1
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+1
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+16
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+16
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | remove leftovers from ast data structuresStefan Biereigel2019-05-271-3/+0
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* | | fix indentation across filesStefan Biereigel2019-05-231-2/+4
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* | | implementation for assignments workingStefan Biereigel2019-05-231-0/+3
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* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-16/+68
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-2/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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