iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
\|
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-1/+2
\|
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+7
\|
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+1
\|
*	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
\|
*	Only use sha1 checksums for names of parametric modules when the verbose ↵	Clifford Wolf	2013-04-26	1	-9/+20
\| \| \| \|	form is to long
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+15
\|
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+9
\|
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-2/+18
\|
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	1	-2/+6
\|
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
\|
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	1	-0/+1
\|
*	initial import	Clifford Wolf	2013-01-05	1	-0/+859