| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 1 | -0/+3 | |
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| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -17/+27 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -16/+68 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -2/+20 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 1 | -9/+17 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -2/+2 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -6/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -113/+99 | |
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| * | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 1 | -3/+105 | |
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| * | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 | |
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| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -3/+28 | |
| | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | |||||
| * | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 | |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -4/+36 | |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -11/+122 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -6/+9 | |
| | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | |||||
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+7 | |
| |\ | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -7/+6 | |
| | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -5/+13 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 1 | -7/+7 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+2 | |
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| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 | |
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| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -2/+7 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -4/+2 | |
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| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -2/+7 | |
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| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 1 | -0/+1 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 | |
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| * | Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() | Clifford Wolf | 2016-08-21 | 1 | -4/+15 | |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 1 | -5/+16 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+1 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+1 | |
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| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -2/+2 | |
| | | | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h | |||||
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+12 | |
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| * | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 1 | -9/+0 | |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
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| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -1/+10 | |
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| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| * | Fixed segfault in AstNode::asReal | Clifford Wolf | 2015-09-25 | 1 | -1/+1 | |
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| * | Fixed AstNode::mkconst_bits() segfault on zero-sized constant | Clifford Wolf | 2015-09-24 | 1 | -1/+1 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -4/+4 | |
| | | | | | Smaller this time | |||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 | |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -0/+1 | |
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| * | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 1 | -2/+6 | |
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| * | Creating $meminit cells in verilog front-end | Clifford Wolf | 2015-02-14 | 1 | -1/+2 | |
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index : iCE40/yosys | |
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