iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
...
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-2/+2
\|
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-1/+1
\|
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26	1	-0/+1
\|
*	Fixed handling of invalid array access in mem2reg code	Clifford Wolf	2014-10-16	1	-0/+1
\|
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21	1	-0/+1
\|
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	1	-0/+4
\|
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18	1	-0/+1
\|
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17	1	-2/+2
\|
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	1	-2/+3
\|
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-0/+4
\|
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-1/+1
\|
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
\|
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-1/+1
\|
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17	1	-0/+1
\|
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16	1	-2/+2
\|
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	1	-0/+1
\|
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14	1	-0/+4
\|
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	1	-0/+2
\|
*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+1
\|
*	further improved const function support	Clifford Wolf	2014-06-07	1	-1/+1
\|
*	improved const function support	Clifford Wolf	2014-06-06	1	-0/+1
\|
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	1	-0/+1
\|
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	1	-3/+3
\|
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	1	-0/+1
\|
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	1	-1/+6
\|
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-1/+1
\|
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+1
\|
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-3/+3
\|
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	1	-0/+3
\|
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	1	-0/+1
\|
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+2
\|
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	1	-1/+2
\|
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-0/+1
\|
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+2
\|
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
\|
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-0/+2
\|
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-1/+1
\|
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-4/+2
\|
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
\|
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-1/+20
\|
*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02	1	-1/+5
\| \| \| \|	fixes)
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-0/+1
\|
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	1	-3/+3
\|
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	1	-0/+1
\|
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-1/+5
\|
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+1
\|
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+3
\|
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-1/+1
\|
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-0/+1
\|
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-3/+3
\|