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* genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
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* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-25/+25
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* verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-0/+35
| | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
| | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
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* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+24
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Merge pull request #2041 from PeterCrozier/structclairexen2020-06-041-0/+2
|\ | | | | Implementation of SV structs.
| * Merge branch 'master' into structPeter Crozier2020-06-031-1/+1
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| * | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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| * | Implement SV structs.Peter Crozier2020-05-081-0/+1
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* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+1
|\ \ \ | |_|/ |/| | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-1/+1
| |/ |/| | | | | Fixes #2058.
* | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-081-3/+4
|\ \ | | | | | | Avoid switch fall-through warnings
| * | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-071-3/+4
| | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-4/+19
|\ \ \ | |/ / |/| | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-1/+7
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+4
| |/ | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-1/+1
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* | frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
|/ | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+4
| | | | Fixes #1819, #1820.
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-3/+128
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-134/+122
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* kernel: use more ID::*Eddie Hung2020-04-021-45/+45
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-102/+101
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-102/+101
| | | | | | | | and RTLIL nodes.
* | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
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* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-7/+11
|\ | | | | Improve specify parser
| * verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
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* | partial rebase of PeterCrozier's enum work onto current masterJeff Wang2020-01-161-2/+6
|/ | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f
* sv: Switch parser to glr, prep for typedefDavid Shah2019-10-031-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* substr() -> compare()Eddie Hung2019-08-071-1/+1
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* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
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* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-1/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-1/+31
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+1
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+1
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-3/+9
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| * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| |\ \ | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-2/+7
| |/ / | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
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* | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
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* | | fix indentation across filesStefan Biereigel2019-05-231-58/+76
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* | | implementation for assignments workingStefan Biereigel2019-05-231-14/+79
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* | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-0/+2
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